Sensing memory cells coupled to different access lines in different blocks of memory cells

ABSTRACT

In an embodiment, a target memory cell in a first block of memory cells of a memory device and a target memory cell in a second block of memory cells of the memory device are sensed concurrently while a read voltage is applied to a selected access line coupled to the target memory cell in the first block of memory cells and while a read voltage is applied to another selected access line coupled to the target memory cell in the second block of memory cells.

FIELD

The present disclosure relates generally to, memory and, in particular,the present disclosure relates to sensing memory cells coupled todifferent data lines in different blocks of memory cells.

BACKGROUND

Memory devices are typically provided as internal, semiconductor,integrated circuits in computers or other electronic devices. There aremany different types of memory, including random-access memory (RAM),read only memory (ROM), dynamic random access memory (DRAM), synchronousdynamic random access memory (SDRAM), and flash memory.

Flash memory devices (e.g., NAND, NOR, etc.) have developed into apopular source of non-volatile memory for a wide range of electronicapplications. Non-volatile memory is memory that can retain its datavalues for some extended period without the application of power. Flashmemory devices typically use a one-transistor memory cell that allowsfor high memory densities, high reliability, and low power consumption.Changes in threshold voltage of the cells, through programming (which issometimes referred to as writing) of charge-storage structures (e.g.,floating gates or charge traps) or other physical phenomena (e.g., phasechange or polarization), determine the data value of each cell. Commonuses for flash memory and other non-volatile memory include personalcomputers, personal digital assistants (PDAs), digital cameras, digitalmedia players, digital recorders, games, appliances, vehicles, wirelessdevices, mobile telephones, and removable memory modules, and the usesfor non-volatile memory continue to expand.

A flash memory device might include a memory array having a plurality ofblocks of memory cells, e.g., sometimes called memory blocks. Forexample, data might be read from a memory array one memory block attime. Data might also be programmed into a memory array one memory blockat a time. Sometimes, for example, a block of memory cells might be aplurality of memory cells that might be erased at once.

A memory block might have a physical block address that denotes thephysical location of the memory block within the memory array, forexample. A memory block might be addressed by a logical block addressreceived from device that is external to the memory device, such as anexternal controller, e.g., sometimes called a host controller. Thememory device, for example, might be configured to translate the logicalblock address into the physical block address of the memory block.

A NAND flash memory device is a common type of flash memory device, socalled for the logical form in which the basic memory cell configurationis arranged. Typically, the array of memory cells for NAND flash memorydevices is arranged such that the control gate of each memory cell of arow of the array is connected together to form an access line, such as aword line. Columns of the array include strings (often termed NANDstrings) of memory cells connected together in series, source to drain,between a pair of select transistors, e.g., a source select transistorand a drain select transistor. Each source select transistor isconnected to a source line, while each drain select transistor isconnected to a data line, such as column bit line. A “column” refers toa group of memory cells that are commonly coupled to a local data line,such as a local bit line. It does not require any particular orientationor linear relationship, but instead refers to the logical relationshipbetween memory cell and data line. Note, for example, that for an arrayhaving a plurality of memory blocks, a string of memory cells of eachmemory block might be selectively coupled to a common data line througha drain select transistor.

For the reasons stated above, and for other reasons stated below whichwill become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art foralternatives to existing methods of reading and/or programming memoryblocks.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified block diagram of a memory system, according to anembodiment.

FIG. 2 is a block diagram illustrating reading portions of differentblocks of a memory array, according to another embodiment.

FIG. 3 is a schematic diagram of a memory block, according to anotherembodiment.

FIG. 4 is a schematic diagram of a memory block, according to anotherembodiment.

FIG. 5A is a block diagram illustrating the states of selector memorycells in different blocks of a memory array, according to anotherembodiment.

FIG. 5B illustrates a timing diagram for a sense operation, according toanother embodiment.

FIG. 6 is a block diagram illustrating the states of selector memorycells a block of a memory array, according to another embodiment.

FIG. 7 is a schematic diagram of a memory block during the sensing ofcertain data lines, according to another embodiment.

FIG. 8 is a schematic diagram of a memory block during the sensing ofcertain data lines of a certain portion of the memory block, accordingto another embodiment.

FIG. 9 is a block diagram illustrating reading portions of differentblocks of a memory array, according to another embodiment.

FIG. 10 is a block diagram illustrating a memory array, during aprogramming operation, according to another embodiment.

FIG. 11 illustrates a timing diagram for a programming operation,according to another embodiment.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings that form a part hereof, and in which is shown, byway of illustration, specific embodiments. In the drawings, likenumerals describe substantially similar components throughout theseveral views. Other embodiments may be utilized and structural,logical, and electrical changes may be made without departing from thescope of the present disclosure. The following detailed description is,therefore, not to be taken in a limiting sense.

FIG. 1 is a simplified block diagram of an electronic device, e.g., anintegrated circuit device, such a memory device 100, in communicationwith a controller 130, such as a memory controller, e.g. a hostcontroller, as part of an electronic system, according to an embodiment.Memory device 100 might be a NAND flash memory device, for example.

Controller 130 might include a processor, for example. Controller 130might be coupled to host, for example, and may receive command signals(or commands), address signals (or addresses), and data signals (ordata) from the host and may output data to the host.

Memory device 100 includes an array of memory cells 104. Memory array104 may be a quasi-two-dimensional (e.g. “two-dimensional”) array. Forexample, a quasi-two-dimensional array might include memory cells (e.g.,series-coupled strings of memory cells) over a surface of asemiconductor, where the surface of the semiconductor lies substantiallyin a single plane. For example, an array may be considered to bequasi-two dimensional when the memory cells are formed in substantiallya single plane, such as a substantially horizontal plane, over asemiconductor, e.g., a planar semiconductor.

As another example, memory array 104 may be a stacked memory array,e.g., often referred to as three-dimensional memory array. For example,one type of three-dimensional memory array might include a plurality ofstacked quasi-two-dimensional arrays. Another type of three-dimensionalmemory array might include pillars of stacked memory elements, such asvertical series-coupled strings of memory cells, e.g., NAND strings.

A row decoder 108 and a column decoder 110 might be provided to decodeaddress signals. Address signals are received and decoded to accessmemory array 104.

Memory device 100 may also include input/output (I/O) control circuitry112 to manage input of commands, addresses, and data to the memorydevice 100 as well as output of data and status information from thememory device 100. An address register 114 is in communication with I/Ocontrol circuitry 112, and row decoder 108 and column decoder 110, tolatch the address signals prior to decoding. A command register 124 isin communication with I/O control circuitry 112 and control logic 116,to latch incoming commands. Control logic 116 controls access to thememory array 104 in response to the commands and generates statusinformation for the external controller 130. The control logic 116 is incommunication with row decoder 108 and column decoder 110 to control therow decoder 108 and column decoder 110 in response to the addresses.

Control logic 116 can be included in controller 130. Controller 130 caninclude, other circuitry, firmware, software, or the like, whether aloneor in combination. Controller 130 can be an external controller (e.g.,in a separate die from the memory array 104, whether wholly or in part)or an internal controller (e.g., included in a same die as the memoryarray 104).

Controller 130 may be configured to cause memory device 100 to performthe methods disclosed herein. For example, controller 130 may beconfigured to cause memory device 100 to sense a target memory cell in afirst block of memory cells of memory array 104 and a target memory cellin a second block of memory cells of memory array 104 concurrently whilea read voltage is being applied to a selected access line coupled to thetarget memory cell in the first block of memory cells and while a readvoltage is being applied to another selected access line coupled to thetarget memory cell in the second block of memory cells. As used herein,multiple acts being performed concurrently will mean that each of theseacts is performed for a respective time period, and each of theserespective time periods overlaps, in part or in whole, with each of theremaining respective time periods. In other words, those acts areconcurrently performed for at least some period of time.

Control logic 116 is also in communication with a cache register 118.Cache register 118 latches data, either incoming or outgoing, asdirected by control logic 116 to temporarily store data while the memoryarray 104 is busy writing or reading, respectively, other data. During awrite operation, data is passed from the cache register 118 to dataregister 120 for transfer to the memory array 104; then new data islatched in the cache register 118 from the I/O control circuitry 112.During a read operation, data is passed from the cache register 118 tothe I/O control circuitry 112 for output to controller 130 andsubsequent output to a host; then new data is passed from the dataregister 120 to the cache register 118. A status register 122 is incommunication with I/O control circuitry 112 and control logic 116 tolatch the status information for output to the controller 130.

Memory device 100 receives control signals at control logic 116 fromcontroller 130 over a control link 132. The control signals may includeat least a chip enable CE#, a command latch enable CLE, an address latchenable ALE, and a write enable WE#. Memory device 100 receives commandsignals (which represent commands), address signals (which representaddresses), and data signals (which represent data) from controller 130over a multiplexed input/output (I/O) bus 134 and outputs data tocontroller 130 over I/O bus 134.

For example, the commands are received over input/output (I/O) pins[7:0] of I/O bus 134 at I/O control circuitry 112 and are written intocommand register 124. The addresses are received over input/output (I/O)pins [7:0] of bus 134 at I/O control circuitry 112 and are written intoaddress register 114. The data are received over input/output (I/O) pins[7:0] for an 8-bit device or input/output (I/O) pins [15:0] for a 16-bitdevice at I/O control circuitry 112 and are written into cache register118. The data are subsequently written into data register 120 forprogramming memory array 104. For another embodiment, cache register 118may be omitted, and the data are written directly into data register120. Data are also output over input/output (I/O) pins [7:0] for an8-bit device or input/output (I/O) pins [15:0] for a 16-bit device.

It will be appreciated by those skilled in the art that additionalcircuitry and signals can be provided, and that the memory device ofFIG. 1 has been simplified. It should be recognized that thefunctionality of the various block components described with referenceto FIG. 1 may not necessarily be segregated to distinct components orcomponent portions of an integrated circuit device. For example, asingle component or component portion of an integrated circuit devicecould be adapted to perform the functionality of more than one blockcomponent of FIG. 1. Alternatively, one or more components or componentportions of an integrated circuit device could be combined to performthe functionality of a single block component of FIG. 1.

Additionally, while specific I/O pins are described in accordance withpopular conventions for receipt and output of the various signals, it isnoted that other combinations or numbers of I/O pins may be used in thevarious embodiments.

FIG. 2 is a block diagram illustrating a memory array 200, during a readoperation. Memory array 200 may be a portion of the memory array 104 ofthe memory device 100 in FIG. 1. Memory array 200 may have a pluralityof memory blocks 210, e.g., including memory blocks 210 ₁ to 210 ₄.

FIG. 3 is a schematic diagram of one such memory block 210, e.g.,configured as a NAND memory block. Memory block 210 may include aplurality of memory cells 302, such as nonvolatile memory cells, betweena select transistor 303, such as a source select transistor, and aselect transistor 304, such as a drain select transistor.

For example, each of a plurality of strings 306 of series-coupled memorycells 302, coupled source to drain, might be between and in series witha select transistor 303 and select transistor 304, where a selecttransistor 303 is configured to selectively couple a string 306 to asource 308 and a select transistor 304 is configured to selectivelycouple that string 306 to a data line, such as a bit line 310, e.g., arespective one of bit lines 310 ₁ to 310 _(M). For example, selecttransistors 304 ₁ to 304 _(M) might be configured to respectively couplea string 306 to bit lines 310 ₁ to 310 _(M).

Each of the plurality of strings 306 might include memory cells 302_(D1) to 302 _(D4), 302₁ to 302 _(N), and 302 _(D5) to 302 _(D8), forexample. Note that each bit line 310 may be commonly coupled to a selecttransistor 304 coupled to a string 306 in each of the memory blocks 210.While the subsequent discussions predominately refer to NAND memorydevices, the present embodiments are not limited to NAND memory devices,but can be used in other memory devices as well.

Select transistors 304 (e.g., select transistors 304 ₁ to 304 _(M))might have control gates commonly coupled to a select line 312, such asa drain select line, while select transistors 303 might have controlgates commonly coupled to a select line 313, such as a source selectline. For example, the select transistors 304 commonly coupled to selectline 312 might form a row of select gates 304, and the selecttransistors 303 commonly coupled to select line 313 might form a row ofselect gates 303.

The memory cells 302 in each of strings 306 may have control gatesrespectively coupled to access lines, such as word lines 315. Forexample, the memory cells 302 _(D1) to 302 _(D4), 302₁ to 302 _(N), and302 _(D5) to 302 _(D8) in each string 306 might be respectively coupledto word lines 315 _(D1) to 315 _(D4), 315₁ to 315 _(N), and 315 _(D5) to315 _(D8).

Word lines 315 _(D1) to 315 _(D4) and 315 _(D5) to 315 _(D8) might bedummy word lines, and the memory cells 302 _(D1) to 302 _(D4) and 302_(D5) to 302 _(D8) respectively coupled to dummy word lines 315 _(D1) to315 _(D4) and 315 _(D5) to 315 _(D8) might be dummy memory cells, e.g.,that are not used for the storage of user data (e.g., from a hostdevice) and/or ECC. However, memory cells 302 ₁ to 302 _(N) may be usedto (e.g., configured to) store user data and the ECC for that user data.For example, memory cells 302 ₁ to 302 _(N) might be referred to asdata-storage memory cells 302 ₁ to 302 _(N) to differentiate them fromthe dummy memory cells 302 _(D1) to 302 _(D4) and 302 _(D5) to 302_(D8). For some embodiments, the memory cells 302 commonly coupled to aword line 315 might be referred to as a row of memory cells, while thosememory cells coupled to a bit line might be referred to as a column ofmemory cells.

A row of memory cells 302 can, but need not include all memory cells 302commonly coupled to a word line 315. Rows of memory cells 302 ofteninclude every other memory cell 302 commonly coupled to a given wordline 315. For example, memory cells 302 commonly coupled to a word line315 and selectively coupled to even bit lines 310 (e.g., bit lines 310₂, 310 ₄, 310 ₆, etc.) may be one row of memory cells 302 (e.g., evenmemory cells), while memory cells 302 commonly coupled to that word line315 and selectively coupled to odd bit lines 304 (e.g., bit lines 310 ₁,310 ₃, 310 ₅, etc.) may be another row of memory cells 302 (e.g., oddmemory cells). Although bit lines 310 ₂-310 ₆ are not expressly depictedin FIG. 3, it is apparent from the figure that the bit lines 310 may benumbered consecutively from bit line 310 ₁ to bit line 310 _(M). Othergroupings of memory cells 302 commonly coupled to a word line 315 mayalso define a row of memory cells 302. For certain memory devices, allmemory cells commonly coupled to a given word line might be deemed aphysical row, while those portions of the physical row that are readduring a single read operation or programmed during a single programoperation (e.g., even or odd memory cells) might be deemed a logicalrow, sometimes referred to as a page.

Typical construction of a memory cell 302 includes a source 330 and adrain 332, a charge-storage structure 334 (e.g., a floating gate, chargetrap, etc.) that can store a charge that determines a data value of thecell, and a control gate 336. The control gates 336 might be coupled to(and in some cases might form a portion of) a word line 315.

Data-storage memory cells 302 ₁ to 302 _(N) might be programmed assingle-level memory cells or multiple-level memory cells. The dummymemory cells 302 _(D3), 302_(D4), 302_(D5), and 302 _(D6), respectivelycommonly coupled to dummy word lines 315 _(D3), 315_(D4), 315 _(D5), and315 _(D6) might be used as (e.g., configured to be used as) selectormemory cells and might be programmed for selecting particular groupingsof data-storage memory cells, commonly coupled to a word line selectedfor reading, for output, e.g., to a page buffer, such as page buffer 220in FIG. 2 that might be a portion of the data register 120 in FIG. 1.For example, dummy memory cells 302 _(D3), 302_(D4), 302_(D5), and 302_(D6) may be referred to as selector memory cells 302 _(D3), 302_(D4),302_(D5), and 302 _(D6), and the dummy access lines (e.g., the dummyword lines 315 _(D3), 315_(D4), 315_(D5), and 315 _(D6)) respectivelycommonly coupled to selector memory cells 302 _(D3), 302_(D4), 302_(D5),and 302 _(D6) may be referred to as selector access lines (e.g.,selector word lines).

Each string 306 might include a pair of selector memory cells coupled inseries to either end of the portion of the string 306 (e.g.,data-storage memory cells 302 ₁ to 302 _(N)) used for storing data. Forexample, series-coupled selector memory cells 302 _(D3) and 302 _(D4)might be coupled in series with memory cell 302 ₁ and series-coupledselector memory cells 302 _(D5) and 302 _(D6) might be coupled in serieswith memory cell 302 _(N). A pair of series-coupled dummy memory cells302 _(D1) and 302 _(D2) might be between and coupled in series withselect transistor 303 and the pair of series-coupled selector memorycells 302 _(D3) and 302 _(D4), and the pair of series-coupled dummymemory cells 302 _(D7) and 302 _(D8) might be between and coupled inseries with select transistor 304 and the pair of series-coupledselector memory cells 302 _(D5) and 302 _(D6).

A pair of selector access lines (e.g., selector word lines 315 _(D3) and315 _(D4)) might be between the word line 315 ₁ commonly coupled to arow of data-storage memory cells 302 ₁ and dummy word line 315 _(D2).Dummy word line 315 _(D1) might be between dummy word line 315 _(D2) andselect line 313. A pair of selector access lines (e.g., selector wordlines 315 _(D5) and 315 _(D6)) might be between the word line 315 _(N)commonly coupled to a row of data-storage memory cells 302 _(N) anddummy word line 315 _(D7). Dummy word line 315 _(D8) might be betweendummy word line 315 _(D7) and select line 312.

A pair of rows of selector memory cells (e.g., the rows of selectormemory cells 302 _(D3) and selector memory cells 302 _(D4)) might bebetween the row of data-storage memory cells 302 ₁ and the row of dummymemory cells 302 _(D2). The row of dummy memory cells 302 _(D1) might bebetween the row of dummy memory cells 302 _(D2) and the row of selecttransistors 303 commonly coupled to select line 313. A pair of rows ofselector memory cells (e.g., the rows of selector memory cells 302 _(D5)and selector memory cells 302 _(D6)) might be between the row ofdata-storage memory cells 302 _(N) and the row of dummy memory cells 302_(D7). The row of dummy memory cells 302 _(D8) might be between the rowof dummy memory cells 302 _(D7) and the row of select transistors 304commonly coupled to select line 312.

A select transistor 304 coupled to a string 306 of memory cells in eachof memory blocks 210 ₁ to 210 ₄ might be coupled to the same bit line310. For example, select transistor 304 ₁ in each of memory blocks 210 ₁to 210 ₄ may be configured to selectively couple a string 306 in arespective one of memory blocks 210 ₁ to 210 ₄ to bit line 310 ₁; selecttransistor 304 ₂ in each of memory blocks 210 ₁ to 210 ₄ may beconfigured to selectively couple a string 306 in a respective one ofmemory blocks 210 ₁ to 210 ₄ to bit line 310 ₂, . . . and selecttransistor 304 _(M) in each of memory blocks 210 ₁ to 210 ₄ may beconfigured to selectively couple a string 306 in a respective one ofmemory blocks 210 ₁ to 210 ₄ to bit line 310 _(M). That is, a string 306in each of memory blocks 210 ₁ to 210 ₄ may be selectively coupled tothe same bit line 310, for example.

FIG. 4 is a schematic diagram of a memory block 210′, e.g., configuredas a NAND memory block, according to another embodiment. For someembodiments, each of the memory blocks 210 ₁ to 210 ₄ in FIG. 2 might beconfigured as memory block 210′. Common numbering is used in FIGS. 3 and4 to denote similar (e.g., the same) components, e.g., where thecommonly numbered components may be as described above in conjunctionwith FIG. 3.

In FIG. 4, the rows of selector memory cells 302 _(D3) and selectormemory cells 302 _(D4) are between the row of data-storage memory cells302 _(N) and the row of selector memory cells 302 _(D5), so that fourrows, e.g. the rows of selector memory cells 302 _(D3) to 302 _(D6), arebetween the row of data-storage memory cells 302 _(N) and the row ofdummy memory cells 302 _(D7). For example, each string 306 includesselector memory cells 302 _(D3) to 302 _(D6) between a data-storagememory cell 302 _(N) and a dummy memory cell 302 _(D7). That is, fourselector access lines (e.g., selector word lines 315 _(D3) to 315 _(D6))might be between the word line 315 _(N) commonly coupled to a row ofdata-storage memory cells 302 _(N) and the dummy word line 315 _(D7),for example.

Note that in each string 306 in FIG. 4, all of the selector memory cells(e.g., selector memory cells 302 _(D3) to 302 _(D6)) are now on thedata-line (e.g., bit-line) side of the data-storage memory cells (e.g.,data-storage memory cells 302 ₁ to 302 _(N)) between the data-storagememory cell 302 _(N) and a select transistor 304 and that only the dummymemory cells 302 _(D1) to 302 _(D2) that are not used as selector memorycells are on the source side of the data-storage memory cells betweenthe data-storage memory cell 302 ₁ and a select transistor 303. Thisacts to reduce the program disturb that might otherwise occur todata-storage memory cell 302 ₁ when programming selector memory cells302 _(D3) and 302 _(D4), when selector memory cells 302 _(D3) and 302_(D4) are on the source side of data-storage memory cell 302 ₁, as shownin FIG. 3, in situations when programming proceeds from the bit-line endof a string toward the source-line end.

For some embodiments, the voltages SEL0 to SEL3 are respectively appliedto selector word lines 315 _(D3) to 315 _(D6), e.g., during a readoperation or a programming operation, as shown in FIGS. 3 and 4. Forexample, the voltages SEL0 to SEL3 might be either a voltage, such asVcc, that is greater than the threshold voltage of a programmed selectormemory cell (e.g., assigned a logic zero) or a voltage, such as Vss,that is less than the threshold voltage of a programmed selector memorycell and greater than the threshold voltage of an erased selector memorycell (e.g., assigned a logic one).

The sets 230 of voltages SEL0 to SEL3 that might be applied to thememory blocks 210 are shown in FIG. 2. For example, sets 230 ₁ to 230 ₄of voltages SEL0 to SEL3 might be respectively applied to memory blocks210 ₁ to 210 ₄.

Each block 210 might be divided into a plurality of portions 240 (e.g.,portions 240 ₁ to 240 ₄) in the row direction, for example, as shown inFIG. 2. For example, each of the rows of memory cells 302 in FIGS. 3 and4 might be divided into the portions 240 ₁ to 240 ₄. For example, eachportion 240 of a row might store four kilobytes of user data and the ECCassociated with that user data. Each of the portions 240 might have thesame size, e.g., each portion 240 of a row might store the same amountof user data and ECC. Alternatively, at least one portion 240 of theplurality of portions 240 might have a different size than the remainingportions 240 of the plurality of portions 240.

Data read from portions 240 ₁ to 240 ₄ may be respectively output to(e.g., sensed by) portions 250 ₁ to 250 ₄ of page buffer 220. Forexample, for some embodiments, portions 250 ₁ to 250 ₄ might sense dataconcurrently. Data read from portion 240 ₁ of memory block 210 ₄,portion 240 ₂ of memory block 210 ₂, portion 240 ₃ of memory block 210₃, and portion 240 ₁ of memory block 210 ₄ might be respectively outputto (e.g., sensed by) portions 250 ₁, 250 ₂, 250 ₃, and 250 ₄ of pagebuffer 220 concurrently. This may be facilitated by programming the rowsof selector memory cells as shown in FIG. 5A. Each portion 250 mightsense a certain amount of data, e.g., four kilobytes of user data plusthe ECC for that user data.

During a read operation, a read voltage might be applied to a selectedword line 315, such as selected word line 315 ₁, in a memory block 210.For example, target memory cells 302 ₁ targeted for reading might becommonly coupled to selected word line 315 ₁ in each of blocks 210.Untargeted memory cells 302 ₁ not targeted for reading might also becommonly coupled to selected word line 315 ₁, for example. That is, forexample, the target memory cells 302 ₁ might be in portions 240 ₄, 240₂, 240 ₃, and 240 ₁ respectively in blocks 210 ₁, 210 ₂, 210 ₃, and 210₄. The untargeted memory cells 302 ₁, however, might be in portions 240₁ to 240 ₃ in block 210 ₁, portions 240 ₁, 240 ₃, and 240 ₄ in block 210₂, portions 240 ₁, 240 ₂, and 240 ₄ in block 210 ₃, and portions 240 ₂to 240 ₄ in block 210 ₄.

While the read voltage is applied to selected word line 315 ₁ in each ofblocks 210, a pass voltage might be applied to unselected word lines 315_(D1), 315_(D2), 315_(D7), 315 _(D8), and 315 ₂ to 315 _(N) in a block210. A row of select transistors 304 commonly coupled to a select line312 in each of blocks 210 may be activated (e.g., turned on) by applyingan activation voltage, such as Vcc, to the select line in each of blocks210 while the pass voltage and the read voltage is applied to each ofthe blocks 210. When the read voltage is greater than a read thresholdvoltage of a memory cell that memory cell is activated (e.g., becomesconductive), whereas when the read voltage is less than the readthreshold voltage of a memory cell that memory cell remains deactivated(e.g., remains non-conducting), e.g., off.

FIG. 5A is a block diagram illustrating the states of the selectormemory cells in the rows of selector memory cells in each of the memoryblocks 210 ₁ to 210 ₄ respectively coupled to selector word lines 315_(D3) to 315 _(D6) in each of the memory blocks 210 ₁ to 210 ₄. Pagebuffer 220, including the portions 250 ₁ to 250 ₄ respectivelycorresponding to the portions 240 ₁ to 240 ₄ of each of the rows ofselector memory cells respectively applied to the selector word lines315 _(D3) to 315 _(D6), is also shown in FIG. 5A.

The voltages SEL0 to SEL3 that might be respectively applied to theselector word lines 315 _(D3) to 315 _(D6) in each of the memory blocks210 are also shown in FIG. 5A. The voltages SEL0 to SEL3 respectivelyapplied to the selector word lines 315 _(D3) to 315 _(D6) in each of thememory blocks 210 might be applied while the read voltage is applied toselected word line 315 ₁ in each of blocks 210, while the pass voltageis applied to unselected word lines 315 _(D1), 315 _(D2), 315 _(D7), 315_(D8), and 315 ₂ to 315 _(N) in each of blocks 210, and while theactivation voltage is applied to the select line 312 in each of blocks210, for example. For some embodiments, the sets 230 ₁ to 230 ₄ ofvoltages SEL0 to SEL3 might be applied concurrently.

In each of blocks 210 ₁ to 210 ₄, the selector memory cells in theportion 240 ₁ of the row of selector memory cells (e.g., the rowselector memory cells 302 _(D3) in FIGS. 3 and 4) coupled to selectorword line 315 _(D3) might be programed and might have, for example, alogic level zero, whereas the memory cells in each of the remainingportions 240 ₂ to 240 ₄ of the row of selector memory cells coupled toselector word line 315 _(D3) might be erased and might have a logiclevel one.

In each of blocks 210 ₁ to 210 ₄, the selector memory cells in theportion 240 ₂ of the row of selector memory cells (e.g., the rowselector memory cells 302 _(D4) in FIGS. 3 and 4) coupled to selectorword line 315 _(D4) might be programed and might have, for example, alogic level zero, whereas the memory cells in each of the remainingportions 240 ₁, 240 ₃, and 240 ₄ of the row of selector memory cellscoupled to selector word line 315 _(D4) might be erased and might have alogic level one.

In each of blocks 210 ₁ to 210 ₄, the selector memory cells in theportion 240 ₃ of the row of selector memory cells (e.g., the rowselector memory cells 302 _(D5) in FIGS. 3 and 4) coupled to selectorword line 315 _(D5) might be programed and might have, for example, alogic level zero, whereas the memory cells in each of the remainingportions 240 ₁, 240 ₂, and 240 ₄ of the row of selector memory cellscoupled to selector word line 315 _(D5) might be erased and might have alogic level one.

In each of blocks 210 ₁ to 210 ₄, the selector memory cells in theportion 240 ₄ of the row of selector memory cells (e.g., the rowselector memory cells 302 _(D6) in FIGS. 3 and 4) coupled to selectorword line 315 _(D6) might be programed and might have, for example, alogic level zero, whereas the memory cells in each of the remainingportions 240 ₁ to 240 ₃ of the row of selector memory cells coupled toselector word line 315 _(D6) might be erased and might have a logiclevel one.

The set 230 ₁ of voltages SEL0 to SEL3 may be applied to the selectorword lines 315 of memory block 210 ₁. The voltages SEL0=Vss, SEL1=Vss,SEL2=Vss, and SEL3=Vcc might be respectively applied to the selectorword lines 315 _(D3), 315_(D4), 315 _(D5), and 315 _(D6) of memory block210 ₁, for example. Voltages of Vss and Vcc can activate (e.g., turn on)all of the erased selector memory cells in memory block 210 ₁. Thevoltage Vcc activates the programmed selector memory cells, e.g.,selector memory cells 302 _(D6) (FIGS. 3 and 4), in the portion 240 ₄ ofthe row of selector memory cells commonly coupled to word line 315 _(D6)in memory block 210 ₁.

The voltage Vss is insufficient to activate the programmed selectormemory cells, e.g., selector memory cells 302 _(D3), 302_(D4), and 302_(D5) (FIGS. 3 and 4), in the portions 240 ₁, 240 ₂, and 240 ₃ of therows of selector memory cells respectively commonly coupled to selectorword lines 315 _(D3), 315_(D4), and 315 _(D5) in memory block 210 ₁ sothat the programmed selector memory cells in the portions 240 ₁, 240 ₂,and 240 ₃ of the rows of memory cells respectively commonly coupled toselector word lines 315 _(D3), 315 _(D4), and 315 _(D5) in memory block210 ₁ are deactivated (e.g., non-conducting).

The programmed selector memory cells that are deactivated isolate thestrings 306 of memory cells in memory block 210 ₁ that include thosedeactivated selector memory cells from their respective data lines andthus prevent the data (e.g., user data and ECC) stored in those strings,e.g., stored in the data-storage memory cells (e.g., data-storage memorycells 302 ₁ to 302 _(N)) of those stings 306, from being output to thepage buffer. That is, the isolated strings are prevented from beingsensed at the page buffer, e.g., by sense amplifiers coupled to the datalines selectively coupled to those strings, for example. Portions 240 ₁,240 ₂, and 240 ₃ of memory block 210 ₁ are isolated, for example,preventing data from portions 240 ₁, 240 ₂, and 240 ₃ of memory block210 ₁ from being respectively output to portions 250 ₁, 250 ₂, and 250 ₃of page buffer 220.

As used herein, isolating a memory cell or string of memory cells from adata line (e.g., a bit line) means to inhibit current flow through thememory cell or string of memory cells to that data line. For example, amemory cell or string of memory cells that is isolated from its bit linemay be an inhibited memory cell or inhibited string of memory cells thatis inhibited from being programmed or read (e.g., sensed). That is,programmed selector memory cells that are deactivated inhibit thestrings of memory cells in memory block that include those deactivatedselector memory cells, for example.

For example, the deactivated selector memory cells electrically isolatethe strings in portions 240 ₁ to 240 ₃ of block 210 ₁ that include thedeactivated selector memory cells from the data lines, e.g., while theselect transistors 304 in portions 240 ₁ to 240 ₃ of block 210 ₁ coupledto the strings that include the deactivated selector memory cells andthat are coupled to those data lines (e.g., the select transistorscoupled between the strings and those data lines) are activated. Theactivated selector memory cells in portion 240 ₄ of block 210 ₁ allowthe strings in portion 240 ₄ of block 210 ₁ that include the activatedselector memory cells to be coupled to data lines through the activatedselect transistors 304 in portion 240 ₄ of block 210 ₁ that are coupledbetween the strings and those data lines.

The set 230 ₂ of voltages SEL0 to SEL3 may be applied to the selectorword lines 315 of memory block 210 ₂. The voltages SEL0=Vss, SEL1=Vcc,SEL2=Vss, and SEL3=Vss might be respectively applied to the selectorword lines 315 _(D3), 315_(D4), 315_(D5), and 315 _(D6) of memory block210 ₂, for example. Voltages of Vss and Vcc can activate all of theerased selector memory cells in memory block 210 ₂. The voltage Vccactivates the programmed selector memory cells, e.g., selector memorycells 302 _(D4) (FIGS. 3 and 4), in the portion 240 ₂ of the row ofselector memory cells commonly coupled to word line 315 _(D4) in memoryblock 210 ₂.

The voltage Vss is insufficient to activate the programmed selectormemory cells, e.g., selector memory cells 302 _(D3), 302_(D5), and 302_(D6) (FIGS. 3 and 4), in the portions 240 ₁, 240 ₃, and 240 ₄ of therows of selector memory cells respectively commonly coupled to selectorword lines 315 _(D3), 315_(D5), and 315 _(D6) in memory block 210 ₂ sothat the programmed selector memory cells in the portions 240 ₁, 240 ₃,and 240 ₄ of the rows of memory cells respectively commonly coupled toword lines 315 _(D3), 315_(D5), and 315 _(D6) in memory block 210 ₂ aredeactivated.

The programmed selector memory cells that are deactivated isolate thestrings 306 of memory cells in memory block 210 ₂ that include thosedeactivated selector memory cells and thus prevent the data (e.g., userdata and ECC) stored in those strings, e.g., stored in the data-storagememory cells (e.g., data-storage memory cells 302 ₁ to 302 _(N)) ofthose stings 306, from being output to the page buffer. That is, thedeactivated strings are prevented from being sensed at the page buffer,e.g., by sense amplifiers coupled to the data lines selectively coupledto those strings, for example. Portions 240 ₁, 240 ₃, and 240 ₄ ofmemory block 210 ₂ are deactivated, for example, preventing data fromportions 240 ₁, 240 ₃, and 240 ₄ of memory block 210 ₂ from beingrespectively output to portions 250 ₁, 250 ₃, and 250 ₄ of page buffer220.

For example, the deactivated selector memory cells electrically isolatethe strings in portions 240 ₁, 240 ₃, and 240 ₄ of block 210 ₂ thatinclude the deactivated selector memory cells from the data lines, e.g.,while the select transistors 304 in portions 240 ₁, 240 ₃, and 240 ₄ ofblock 210 ₂ coupled to the strings that include the deactivated selectormemory cells and that are coupled to those data lines (e.g., the selecttransistors coupled between the strings and those data lines) areactivated. The activated selector memory cells in portion 240 ₂ of block210 ₂ allow the strings in portion 240 ₂ of block 210 ₂ that include theactivated selector memory cells to be coupled to data lines through theactivated select transistors 304 in portion 240 ₂ of block 210 ₂ thatare coupled between the strings and those data lines.

The set 230 ₃ of voltages SEL0 to SEL3 may be applied to the selectorword lines 315 of memory block 210 ₃. The voltages SEL0=Vss, SEL1=Vss,SEL2=Vcc, and SEL3=Vss might be respectively applied to the selectorword lines 315 _(D3), 315 _(D4), 315 _(D5), and 315 _(D6) of memoryblock 210 ₃, for example. Voltages of Vss and Vcc can activate all ofthe erased selector memory cells in memory block 210 ₃. The voltage Vccactivates the programmed selector memory cells, e.g., selector memorycells 302 _(D5) (FIGS. 3 and 4), in the portion 240 ₃ of the row ofselector memory cells commonly coupled to word line 315 _(D5) in memoryblock 210 ₃.

The voltage Vss is insufficient to activate the programmed selectormemory cells, e.g., selector memory cells 302 _(D3), 302_(D4), and 302_(D6) (FIGS. 3 and 4), in the portions 240 ₁, 240 ₂, and 240 ₄ of therows of selector memory cells respectively commonly coupled to selectorword lines 315 _(D3), 315_(D4), and 315 _(D6) in memory block 210 ₃ sothat the programmed selector memory cells in the portions 240 ₁, 240 ₂,and 240 ₄ of the rows of memory cells respectively commonly coupled toword lines 315 _(D3), 315_(D4), and 315 _(D6) in memory block 210 ₃ aredeactivated.

The programmed selector memory cells that are deactivated isolate thestrings 306 of memory cells in memory block 210 ₃ that include thosedeactivated selector memory cells and thus prevent the data (e.g., userdata and ECC) stored in those strings, e.g., stored in the data-storagememory cells (e.g., data-storage memory cells 302 ₁ to 302 _(N)) ofthose stings 306, from being output to the page buffer. That is, thedeactivated strings are prevented from being sensed at the page buffer,e.g., by sense amplifiers coupled to the data lines selectively coupledto those strings, for example. Portions 240 ₁, 240 ₂, and 240 ₄ ofmemory block 210 ₃ are deactivated, for example, preventing data fromportions 240 ₁, 240 ₂, and 240 ₄ of memory block 210 ₃ from beingrespectively output to portions 250 ₁, 250 ₂, and 250 ₄ of page buffer220.

For example, the deactivated selector memory cells electrically isolatethe strings in portions 240 ₁, 240 ₂, and 240 ₄ of block 210 ₃ thatinclude the deactivated selector memory cells from the data lines, e.g.,while the select transistors 304 in portions 240 ₁, 240 ₂, and 240 ₄ ofblock 210 ₃ coupled to the strings that include the deactivated selectormemory cells and that are coupled to those data lines (e.g., the selecttransistors coupled between the strings and those data lines) areactivated. The activated selector memory cells in portion 240 ₃ of block210 ₃ allow the strings in portion 240 ₃ of block 210 ₃ that include theactivated selector memory cells to be coupled to data lines through theactivated select transistors 304 in portion 240 ₃ of block 210 ₃ thatare coupled between the strings and those data lines.

The set 230 ₄ of voltages SEL0 to SEL3 may be applied to the selectorword lines 315 of memory block 210 ₄. The voltages SEL0=Vcc, SEL1=Vss,SEL2=Vss, and SEL3=Vss might be respectively applied to the selectorword lines 315 _(D3), 315_(D4), 315_(D5), and 315 _(D6) of memory block210 ₄, for example. Voltages of Vss and Vcc can activate all of theerased selector memory cells in memory block 210 ₄. The voltage Vccactivates the programmed selector memory cells, e.g., selector memorycells 302 _(D3) (FIGS. 3 and 4), in the portion 240 ₁ of the row ofselector memory cells commonly coupled to word line 315 _(D3) in memoryblock 210 ₄.

The voltage Vss is insufficient to activate the programmed selectormemory cells, e.g., selector memory cells 302 _(D4), 302 _(D5), and 302_(D6) (FIGS. 3 and 4), in the portions 240 ₂, 240 ₃, and 240 ₄ of therows of selector memory cells respectively commonly coupled to selectorword lines 315 _(D4), 315_(D5), and 315 _(D6) in memory block 210 ₄ sothat the programmed selector memory cells in the portions 240 ₂, 240 ₃,and 240 ₄ of the rows of memory cells respectively commonly coupled toword lines 315 _(D4), 315 _(D5), and 315 _(D6) in memory block 210 ₄ aredeactivated.

The programmed selector memory cells that are deactivated isolate thestrings 306 of memory cells in memory block 210 ₄ that include thosedeactivated selector memory cells and thus prevent the data (e.g., userdata and ECC) stored in those strings, e.g., stored in the data-storagememory cells (e.g., data-storage memory cells 302 ₁ to 302 _(N)) ofthose stings 306, from being output to the page buffer. That is, thedeactivated strings are prevented from being sensed at the page buffer,e.g., by sense amplifiers coupled to the data lines selectively coupledto those strings, for example. Portions 240 ₂, 240 ₃, and 240 ₄ ofmemory block 210 ₄ are deactivated, for example, preventing data fromportions 240 ₂, 240 ₃, and 240 ₄ of memory block 210 ₄ from beingrespectively output to portions 250 ₂, 250 ₃, and 250 ₄ of page buffer220.

For example, the deactivated selector memory cells electrically isolatethe strings in portions 240 ₂ to 240 ₄ of block 210 ₄ that include thedeactivated selector memory cells from the data lines, e.g., while theselect transistors 304 in portions 240 ₂ to 240 ₄ of block 210 ₄ coupledto the strings that include the deactivated selector memory cells andthat are coupled to those data lines (e.g., the select transistorscoupled between the strings and those data lines) are activated. Theactivated selector memory cells in portion 240 ₁ of block 210 ₄ allowthe strings in portion 240 ₁ of block 210 ₄ that include the activatedselector memory cells to be coupled to data lines through the activatedselect transistors 304 in portion 240 ₁ of block 210 ₄ that are coupledbetween the strings and those data lines.

Note that select transistors 304 in portion 240 ₄ of block 210 ₁ arecoupled between the strings 306 in portion 240 ₄ of block 210 ₁ and datalines, such as first bit lines 310, that pass through portion 240 ₄ ofeach of blocks 210 ₁ to 210 ₄, that the select transistors 304 inportion 240 ₄ of block 210 ₂ are coupled between the strings 306 inportion 240 ₄ of block 210 ₂ and the first bit lines 310, that theselect transistors 304 in portion 240 ₄ of block 210 ₃ are coupledbetween the strings 306 in portion 240 ₄ of block 210 ₃ and the firstbit lines 310, and that the select transistors 304 in portion 240 ₄ ofblock 210 ₄ are coupled between the strings 306 in portion 240 ₄ ofblock 210 ₄ and the first bit lines 310.

Note, also, that the select transistors 304 in portion 240 ₃ of block210 ₁ are coupled between the strings 306 in portion 240 ₃ of block 210₁ and data lines, such as second bit lines 310, that pass throughportion 240 ₃ of each of blocks 210 ₁ to 210 ₄, that the selecttransistors 304 in portion 240 ₃ of block 210 ₂ are coupled between thestrings 306 in portion 240 ₃ of block 210 ₂ and the second bit lines310, that the select transistors 304 in portion 240 ₃ of block 210 ₃ arecoupled between the strings 306 in portion 240 ₃ of block 210 ₃ and thesecond bit lines 310, and that the select transistors 304 in portion 240₃ of block 210 ₄ are coupled between the strings 306 in portion 240 ₃ ofblock 210 ₄ and the second bit lines 310.

Note that the select transistors 304 in portion 240 ₂ of block 210 ₁ arecoupled between the strings 306 in portion 240 ₂ of block 210 ₁ and datalines, such as third bit lines 310, that pass through portion 240 ₂ ofeach of blocks 210 ₁ to 210 ₄, that the select transistors 304 inportion 240 ₂ of block 210 ₂ are coupled between the strings 306 inportion 240 ₂ of block 210 ₂ and the third bit lines 310, that theselect transistors 304 in portion 240 ₂ of block 210 ₃ are coupledbetween the strings 306 in portion 240 ₂ of block 210 ₃ and the thirdbit lines 310, and that the select transistors 304 in portion 240 ₂ ofblock 210 ₄ are coupled between the strings 306 in portion 240 ₂ ofblock 210 ₄ and the third bit lines 310.

Note that the select transistors 304 in portion 240 ₁ of block 210 ₁ arecoupled between the strings 306 in portion 240 ₁ of block 210 ₁ and datalines, such as fourth bit lines 310, that pass through portion 240 ₁ ofeach of blocks 210 ₁ to 210 ₄, that the select transistors 304 inportion 240 ₁ of block 210 ₂ are coupled between the strings 306 inportion 240 ₁ of block 210 ₂ and the fourth bit lines 310, that theselect transistors 304 in portion 240 ₁ of block 210 ₃ are coupledbetween the strings 306 in portion 240 ₁ of block 210 ₃ and the fourthbit lines 310, and that the select transistors 304 in portion 240 ₁ ofblock 210 ₄ are coupled between the strings 306 in portion 240 ₁ ofblock 210 ₄ and the fourth bit lines 310.

In the example of FIG. 5A, the only portions 240 of the rows of selectormemory cells that are activated are the portion 240 ₄ of the row ofselector memory cells commonly coupled to word line 315 _(D6) in memoryblock 210 ₁, the portion 240 ₂ of the row of selector memory cellscommonly coupled to word line 315 _(D4) in memory block 210 ₂, theportion 240 ₃ of the row of selector memory cells commonly coupled toword line 315 _(D5) in memory block 210 ₃, and the portion 240 ₁ of therow of selector memory cells commonly coupled to word line 315 _(D3) inmemory block 210 ₄. As such, the only data that is output from memoryblocks 210 ₁, 210 ₂, 210 ₃, and 210 ₄ is respectively from portion 240 ₄of block 210 ₁, portion 240 ₂ of block 210 ₂, portion 240 ₃ of block 210₃, and portion 240 ₁ of block 210 ₄. For example, this might allow data(e.g., user data and ECC) to be read concurrently from the differentmemory blocks 210 ₁, 210 ₂, 210 ₃, and 210 ₄, e.g., where the portions240 ₁ to 240 ₄ have the same address, such as the same page address.That is, target memory cells respectively in the portions 240 ₁ to 240 ₄might be addressed by the same (e.g., a common) page address, forexample.

The data from the different memory blocks 210 ₁, 210 ₂, 210 ₃, and 210 ₄might be respectively output concurrently to the portions 250 ₄, 250 ₂,250 ₃, and 250 ₁, for example. That is, the data from the differentmemory blocks 210 ₁, 210 ₂, 210 ₃, and 210 ₄ may be respectively sensedconcurrently at the portions 250 ₄, 250 ₂, 250 ₃, and 250 ₁, e.g., inresponse to a sense amplifier enable signal commonly received atportions 250 ₄, 250 ₂, 250 ₃, and 250 ₁.

The data from the different memory blocks 210 ₁, 210 ₂, 210 ₃, and 210 ₄that is respectively sensed concurrently at the portions 250 ₄, 250 ₂,250 ₃, and 250 ₁ might be in response to applying a read voltageconcurrently to the selected word line 302 ₁ in each of the differentmemory blocks 210 ₁, 210 ₂, 210 ₃, and 210 ₄, for example, while thepass voltages are applied concurrently to the unselected word lines 315_(D1), 315_(D2), 315_(D7), 315_(D8), and 315 ₂ to 315 _(N) in each ofthe different memory blocks 210 ₁, 210 ₂, 210 ₃, and 210 ₄, while anactivation voltage is applied concurrently to the select line 312 ineach of the different memory blocks 210 ₁, 210 ₂, 210 ₃, and 210 ₄, andwhile the sets 230 ₁ to 230 ₄ of voltages SEL0 to SEL3 are appliedconcurrently to the selector word lines 315 _(D3), 315_(D4), 315_(D5),and 315 _(D6) in the different memory blocks 210 ₁, 210 ₂, 210 ₃, and210 ₄. For example, the read voltage, pass voltages, the activationvoltage, and the sets 230 ₁ to 230 ₄ of voltages SEL0 to SEL3 might beapplied concurrently to the different memory blocks 210 ₁, 210 ₂, 210 ₃,and 210 ₄.

For the data to be output from portion 240 ₄ of block 210 ₁, portion 240₂ of block 210 ₂, portion 240 ₃ of block 210 ₃, and portion 240 ₁ ofblock 210 ₄ concurrently, the activation voltage may be applied to theselect line 312 in each of the different memory blocks 210 ₁, 210 ₂, 210₃, and 210 ₄ concurrently, and the bit lines 310 coupled to the strings306 in portions 240 ₁ to 240 ₄ may be selected concurrently, e.g., bitlines 310 ₁ to 310 _(M) may be selected concurrently. Note thatdifferent subsets of the bit lines 310 ₁ to 310 _(M) might berespectively selectively coupled to the strings 306 in portions 240 ₁ to240 ₄. For example, the subset of the bit lines 310 ₁ to 310 _(M)coupled to sense amplifiers in portion 250 ₁ of page buffer 220 (e.g.,the fourth bit lines 310 that pass through portions 240 ₁), the subsetof the bit lines 310 ₁ to 310 _(M) coupled to sense amplifiers inportion 250 ₂ of page buffer 220 (e.g., the third bit lines 310 thatpass through portions 240 ₂), the subset of the bit lines 310 ₁ to 310_(M) coupled to sense amplifiers in portion 250 ₃ of page buffer 220(e.g., the second bit lines 310 that pass through portions 240 ₃), andthe subset of the bit lines 310 ₁ to 310 _(M) coupled to senseamplifiers in portion 250 ₄ of page buffer 220 (e.g., the first bitlines 310 that pass through portions 240 ₄) may be respectively coupledto the strings 306 in portions 240 ₁, 240 ₂, 240 ₃, and 240 ₄.

Note that the portion 240 ₁ of each of blocks 210 ₁ to 210 ₃ is notselected, but that a read voltage might be applied to the selected wordline 315 ₁ in each of blocks 210 ₁ to 210 ₃, that the select transistors304 in each of blocks 210 ₁ to 210 ₃ are activated, and that the bitlines coupled to the select transistors 304 that are coupled to strings306 in the portion 240 ₁ of each of blocks 210 ₁ to 210 ₃ are selected.Also note that unselected memory cells 302 ₁ are commonly coupled theselected word line 315 ₁ in each of blocks 210 ₁ to 210 ₃. Thedeactivated selector memory cells in the portion 240 ₁ of each of blocks210 ₁ to 210 ₃ isolate the unselected memory cells 302 ₁ that arecommonly coupled the selected word line 315 ₁ in each of blocks 210 ₁ to210 ₃ from the selected bit lines that are coupled to the selecttransistors 304 that are coupled to strings 306 that include theunselected memory cells 302 ₁ and the deactivated selector memory cells.A selector memory cell is used to isolate an unselected memory cellcoupled to a selected word line from a selected bit line, in that theselect transistor coupled between the selected bit line and the string306 that includes the selector memory cell and the unselected memorycell is activated.

The row of dummy memory cells 302 _(D1) commonly coupled to dummy wordline 315 _(D1) and the row of dummy memory cells 302 _(D2) commonlycoupled to dummy word line 315 _(D2) in FIG. 3 might be respectivelyused as selector memory cells instead of the row of dummy memory cells302 _(D3) commonly coupled to dummy word line 315 _(D3) and the row ofdummy memory cells 302 _(D4) commonly coupled to dummy word line 315_(D4), for some embodiments. For example, the voltages SEL0 and SEL1might be respectively applied to dummy word lines 315 _(D1) and 315_(D2), where the row of dummy memory cells 302 _(D1) in each of theblocks 210 ₁ to 210 ₄ might be programmed as shown in FIG. 5A for therow of memory cells memory cells 302 _(D3) coupled to word line 315_(D3) in each of the blocks 210 ₁ to 210 ₄ and the row of dummy memorycells 302 _(D2) in each of the blocks 210 ₁ to 210 ₄ might be programmedas shown in FIG. 5A for the row of memory cells 302 _(D4) coupled toword line 315 _(D4) in each of the blocks 210 ₁ to 210 ₄.

For some embodiments, the row of dummy memory cells 302 _(D7) commonlycoupled to dummy word line 315 _(D7) and the row of dummy memory cells302 _(D8) commonly coupled to dummy word line 315 _(D8) in FIG. 3 mightbe respectively used as selector memory cells instead of the row ofdummy memory cells 302 _(D5) commonly coupled to dummy word line 315_(D5) and the row of dummy memory cells 302 _(D6) commonly coupled todummy word line 315 _(D6). For example, the voltages SEL2 and SEL3 mightbe respectively applied to dummy word lines 315 _(D7) and 315 _(D8),where the row of dummy memory cells 302 _(D7) in each of the blocks 210₁ to 210 ₄ might be programmed as shown in FIG. 5A for the row of memorycells memory cells 302 _(D5) coupled to word line 315 _(D5) in each ofthe blocks 210 ₁ to 210 ₄ and the row of dummy memory cells 302 _(D8) ineach of the blocks 210 ₁ to 210 ₄ might be programmed as shown in FIG.5A for the row of memory cells memory cells 302 _(D6) coupled to wordline 315 _(D6) in each of the blocks 210 ₁ to 210 ₄.

For some embodiments, the row of dummy memory cells 302 _(D7) commonlycoupled to dummy word line 315 _(D7) and the row of dummy memory cells302 _(D8) commonly coupled to dummy word line 315 _(D8) in FIG. 4 mightbe respectively used as selector memory cells instead of the row ofdummy memory cells 302 _(D3) commonly coupled to dummy word line 315_(D3) and the row of dummy memory cells 302 _(D4) commonly coupled todummy word line 315 _(D4), and the row of dummy memory cells 302 _(D5)commonly coupled to dummy word line 315 _(D5) and the row of dummymemory cells 302 _(D6) commonly coupled to dummy word line 315 _(D6) inFIG. 4 might be respectively used as selector memory cells instead ofthe row of dummy memory cells 302 _(D3) commonly coupled to dummy wordline 315 _(D3) and the row of dummy memory cells 302 _(D4) commonlycoupled to dummy word line 315 _(D4). For example, the voltages SEL0 toSEL3 might be respectively applied to dummy word lines 315 _(D5) to 315_(D8) in FIG. 4, where the row of dummy memory cells 302 _(D5) in eachof the blocks 210 ₁ to 210 ₄ might be programmed as shown in FIG. 5A forthe row of “dummy memory cells 302 _(D3) coupled to word line 315 _(D3)in each of the blocks 210 ₁ to 210 ₄, where the row of dummy memorycells 302 _(D6) in each of the blocks 210 ₁ to 210 ₄ might be programmedas shown in FIG. 5A for the row of dummy memory cells 302 _(D4) coupledto word line 315 _(D4) in each of the blocks 210 ₁ to 210 ₄, where therow of dummy memory cells 302 _(D7) in each of the blocks 210 ₁ to 210 ₄might be programmed as shown in FIG. 5A for the row of dummy memorycells memory cells 302 _(D5) coupled to word line 315 _(D5) in each ofthe blocks 210 ₁ to 210 ₄, and where the row of dummy memory cells 302_(D8) in each of the blocks 210 ₁ to 210 ₄ might be programmed as shownin FIG. 5A for the row of dummy memory cells memory cells 302 _(D6)coupled to word line 315 _(D6) in each of the blocks 210 ₁ to 210 ₄, andwhere the row of dummy memory cells 302 _(D4) commonly coupled to wordline 315 _(D4), the row of dummy memory cells 302 _(D3) commonly coupledto word line 315 _(D3), the row of dummy memory cells 302 _(D2) commonlycoupled to word line 315 _(D2), and the row of dummy memory cells 302_(D1) commonly coupled to word line 315 _(D1) in FIG. 4 in each of theblocks 210 ₁ to 210 ₄ are not used as selector memory cells.

Each of the different memory blocks 210 ₁, 210 ₂, 210 ₃, and 210 ₄ mighthave a different physical block address, but each of the portions 240 ₄of block 210 ₁, 240 ₂ of block 210 ₂, 240 ₃ of block 210 ₃, and 240 ₁ ofblock 210 ₄ might have the same page (e.g., logical row) address. Forexample, when each of the portions 240 ₄ of block 210 ₁, 240 ₂ of block210 ₂, 240 ₃ of block 210 ₃, and 240 ₁ of block 210 ₄ have the same pageaddress, the data from the respective portions 240 ₁, 240 ₂, 240 ₃, and240 ₄, might be respectively concurrently sensed from portions 250 ₁,250 ₂, 250 ₃, and 250 ₄ of page buffer 220, e.g., in response to a senseamplifier enable signal being received concurrently at portions 250 ₁,250 ₂, 250 ₃, and 250 ₄ of page buffer 220.

Alternatively, each of the different memory blocks 210 ₁, 210 ₂, 210 ₃,and 210 ₄ might have a different physical block address, and each of theportions 240 ₄ of block 210 ₁, 240 ₂ of block 210 ₂, 240 ₃ of block 210₃, and 240 ₁ of block 210 ₄ might have a different page address. Forexample, when each of the portions 240 ₄ of block 210 ₁, 240 ₂ of block210 ₂, 240 ₃ of block 210 ₃, and 240 ₁ of block 210 ₄ has a differentpage address, the data from the respective portions 240 ₁, 240 ₂, 240 ₃,and 240 ₄ might be sensed from portions 250 ₁, 250 ₂, 250 ₃, and 250 ₄of page buffer 220 individually one at a time, e.g., in response to asense amplifier enable signal being received at respective ones of theportions 250 ₁, 250 ₂, 250 ₃, and 250 ₄. For example, target memorycells in the portions 240 ₁, 240 ₂, 240 ₃, and 240 ₄ might berespectively addressed by different page addresses. Data might be sensedsequentially from portions 250 ₁, 250 ₂, 250 ₃, and 250 ₄ in response tosense amplifier enable signals being received sequentially at portions250 ₁, 250 ₂, 250 ₃, and 250 ₄, for example.

For example, block 210 ₄ and the page corresponding to portion 240 ₁ ofblock 210 ₄ might be selected, while the remaining blocks 210 ₁ to 210 ₃remain unselected. Subsequently, portion 250 ₁ may be sensed in responseto a sense amplifier enable signal received concurrently at the senseamplifiers in portion 250 ₁ that are coupled to the pre-charged datalines.

After sensing portion 250 ₁ of block 210 ₄, block 210 ₂ and the pagecorresponding to portion 240 ₂ of block 210 ₂ might be selected, whilethe remaining blocks 210 ₁, 210 ₃, and 210 ₄ remain unselected. Then,all of the data lines coupled to the memory cells in portion 240 ₂ andcoupled to sense amplifiers in the portion 250 ₂, corresponding toportion 240 ₂, might be pre-charged, while the data lines coupled to thememory cells in remaining portions 240 ₁, 240 ₃, and 240 ₄ might remainuncharged. Subsequently, portion 250 ₂ may be sensed in response to asense amplifier enable signal received concurrently at the senseamplifiers in portion 250 ₂ that are coupled to the pre-charged datalines.

After sensing portion 250 ₂ of block 210 ₂, block 210 ₃ and the pagecorresponding to portion 240 ₃ of block 210 ₃ might be selected, whilethe remaining blocks 210 ₁, 210 ₂, and 210 ₄ remain unselected. Then,all of the data lines coupled to the memory cells in portion 240 ₃ andcoupled to sense amplifiers in the portion 250 ₃, corresponding toportion 240 ₃, might be pre-charged, while the data lines coupled to thememory cells in remaining portions 240 ₁, 240 ₂, and 240 ₄ might remainuncharged. Subsequently, portion 250 ₃ may be sensed in response to asense amplifier enable signal received concurrently at the senseamplifiers in portion 250 ₃ that are coupled to the pre-charged datalines.

After sensing portion 250 ₃ of block 210 ₃, block 210 ₁ and the pagecorresponding to portion 240 ₄ of block 210 ₁ might be selected, whilethe remaining blocks 210 ₂ to 210 ₄ remain unselected. Then, all of thedata lines coupled to the memory cells in portion 240 ₄ and coupled tosense amplifiers in the portion 250 ₄, corresponding to portion 240 ₄,might be pre-charged, while the data lines coupled to the memory cellsin remaining portions 240 ₂ to 240 ₄ might remain uncharged.Subsequently, portion 250 ₄ may be sensed in response to a senseamplifier enable signal received concurrently at the sense amplifiers inportion 250 ₄ that are coupled to the pre-charged data lines.

FIG. 5B presents a timing diagram for an example where portion 240 ₁ ofblock 210 ₄ and portion 240 ₂ of block 210 ₂ have different pageaddresses and are sensed individually one at a time. For example, asense (e.g., read) operation might commence by memory device 100(FIG. 1) receiving, e.g., from controller 130, an input signal 560 thatmight include a read command 562 followed in sequence by addresses 564 ₁to 564 ₂, where each address 564 comprises a block and a page address.That is, the page address for block 210 ₄ might address portion 240 ₁ ofblock 210 ₄, and the page address for block 210 ₂ might address portion240 ₂ of block 210 ₂, for example.

During the read operation, the select line 312 (e.g., the drain selectline) and the select line 313 (e.g., the source select line) (FIGS. 3and 4) in blocks 210 ₄ and 210 ₂ might respectively receive voltages 570₁ and 570 ₂. While read command 562 and addresses 564 are beingreceived, voltages 570 ₁ and 570 ₂ might be at a voltage level, such asVss, that is insufficient to activate the select transistors 304 (e.g.,the drain select transistors) coupled to select lines 312 and the selecttransistors 303 (e.g., the source select transistors) coupled to selectlines 313.

The unselected word lines (e.g., unselected word lines 315 _(D1),315_(D2), 315_(D7), 315_(D8), and 315 ₂ to 315 _(N)) in blocks 210 ₄ and210 ₂ might respectively receive voltages 572 ₁ and 572 ₂. While readcommand 562 and addresses 564 are being received, voltages 572 ₁ and 572₂ might be at a voltage level, such as Vss. Selected word lines (e.g.,selected word line 315 ₁) in blocks 210 ₄ and 210 ₂ might respectivelyreceive voltages 574 ₁ and 574 ₂ that might be at a voltage level, suchas Vss, while read command 562 and addresses 564 are being received.

The bit lines coupled to portion 250 ₁ of page buffer 220 might receivea voltage 580 ₁, and the bit lines coupled to portion 250 ₂ of pagebuffer 220 might receive a voltage 580 ₂. While read command 562 andaddresses 564 are being received, voltages 580 ₁ and 580 ₂ might be at apre-charge voltage level, such as a pre-charge voltage level Vpre, sothat the bit lines coupled to portions 250 ₁ and 250 ₂ are pre-chargedto the pre-charge voltage level Vpre.

Portions 250 ₁ and 250 ₂ of page buffer 220 might respectively receivesense enable signals 582 ₁ and 582 ₂. While read command 562 andaddresses 564 are being received, sense enable signals 582 ₁ and 582 ₂might be at a voltage level, such as Vss, that is insufficient to enableportions 250 ₁ and 250 ₂ of page buffer 220 for sensing the bit lines.

After the address 564, including the address of final page (e.g.,address 564 ₂) to be sensed, is received, portion 240 ₁ of block 210 ₄is sensed. That is, the voltages 570 ₁, 572 ₁, and 574 ₁ arerespectively concurrently increased from the voltage level Vss to avoltage level, such as Vcc, that activates the select transistors (e.g.,the source select transistors and the drain select transistors) in block210 ₄, from the voltage level Vss to a pass voltage level, such asVpass_read, that activates the memory cells coupled to the unselectedword lines, and from the voltage level Vss to a read voltage level, suchas Vread. If the read voltage level is insufficient to activate thememory cells coupled to the selected word line, the voltage 580 ₁ of thebit lines coupled to portion 250 ₁ of page buffer 220 may remain at thepre-charge voltage level Vpre, whereas if the read voltage level issufficient activate the memory cells coupled to the selected word line,the voltage 580 ₁ may discharge from the pre-charge voltage level Vpre.Subsequently, the sense enable signal 582 ₁ may be increased from thevoltage level Vss to a voltage level, such as Vcc, sufficient to enablesensing of the bit lines coupled to portion 250 ₁ of page buffer 220.

Note that during the sensing of portion 240 ₁ of block 210 ₄, thevoltages SEL0=Vcc, SEL1=Vss, SEL2=Vss, and SEL3=Vss might berespectively applied to the selector word lines 315 _(D3), 315 _(D4),315_(D5), and 315 _(D6) of memory block 210 ₄, as shown in FIG. 5A. Alsoduring the sensing of portion 240 ₁ of block 210 ₄, the voltage 570 ₂ isat the voltage level Vss so that the source select transistors and thedrain select transistors in block 210 ₂ are deactivated, preventing anycurrent on the bit lines coupled to portion 250 ₁ of page buffer 220from the strings in block 210 ₂. Also during the sensing of portion 240₁ of block 210 ₄, the voltage of select enable signal 582 ₂ is at thevoltage level Vss so that the portion 250 ₂ of page buffer 220 is notenabled for sensing. After the portion 240 ₁ of block 210 ₄ is sensed,the voltages 570 ₁, 572 ₁, 574 ₁ and the voltage of sense enable signal582 ₁ are returned to the voltage level Vss, so that the source selecttransistors and the drain select transistors in block 210 ₄ aredeactivated and so the portion 250 ₁ of page buffer 220 is no longerenabled for sensing.

After portion 240 ₁ of block 210 ₄ is sensed and the voltages 570 ₁, 572₁, 574 ₁ and the voltage of sense enable signal 582 ₁ are returned tothe voltage level Vss, portion 240 ₂ of block 210 ₂ is sensed. That is,the voltages 570 ₂, 572 ₂, and 574 ₂ are respectively concurrentlyincreased from the voltage level Vss to a voltage level, such as Vcc,that activates the select transistors (e.g., the source selecttransistors and the drain select transistors) in block 210 ₂, from thevoltage level Vss to a pass voltage level, such as Vpass_read, thatactivates the memory cells coupled to the unselected word lines, andfrom the voltage level Vss to a read voltage level, such as Vread. Ifthe read voltage level is insufficient activate the memory cells coupledto the selected word line, the voltage 580 ₂ of the bit lines coupled toportion 250 ₂ of page buffer 220 may remain at the pre-charge voltagelevel Vpre, whereas if the read voltage level is sufficient activate thememory cells coupled to the selected word line, the voltage 580 ₂ maydischarge from the pre-charge voltage level Vpre. Subsequently, thesense enable signal 582 ₂ may be increased from the voltage level Vss toa voltage level, such as Vcc, sufficient to enable sensing of the bitlines coupled to portion 250 ₂ of page buffer 220.

Note that during the sensing of portion 240 ₂ of block 210 ₂, thevoltages SEL0=Vss, SEL1=Vcc, SEL2=Vss, and SEL3=Vss might berespectively applied to the selector word lines 315 _(D3), 315_(D4),315_(D5), and 315 _(D6) of memory block 210 ₂, as shown in FIG. 5A. Alsoduring the sensing of portion 240 ₂ of block 210 ₂, the voltage 570 ₁ isat the voltage level Vss so that the source select transistors and thedrain select transistors in block 210 ₄ are deactivated, preventing anycurrent on the bit lines coupled to portion 250 ₂ of page buffer 220from the strings in block 210 ₄; Also during the sensing of portion 240₂ of block 210 ₂, the voltage of select enable signal 582 ₁ is at thevoltage level Vss so that the portion 250 ₁ of page buffer 220 is notenabled for sensing. After the portion 240 ₂ of block 210 ₂ is sensed,the voltages 570 ₂, 572 ₂, 574 ₂ and the voltage of sense enable signal582 ₂ are returned to the voltage level Vss, so that the source selecttransistors and the drain select transistors in block 210 ₂ aredeactivated and so the portion 250 ₂ of page buffer 220 is no longerenabled for sensing.

The selector memory cells might be used to select multiple portions of asingle memory block for reading. For example, portions 240 ₁ and 240 ₂of memory block 210 ₁ might be selected for reading, while the remainingportions 240 ₃ and 240 ₄ of memory block 210 ₁ and the portions 240 ₂ to240 ₄ of the remaining memory blocks 210 ₂ to 210 ₄ are unselected.Portions 240 ₁ and 240 ₂ of memory block 210 ₁ might be selected byrespectively applying the voltages SEL0=Vcc, SEL1=Vcc, SEL2=Vss, andSEL3=Vss to the selector word lines 315 _(D3), 315_(D4), 315_(D5), and315 _(D6) of memory block 210 ₁, as programmed in FIG. 6, for example.That is, SEL0=Vcc, SEL1=Vcc, SEL2=Vss, and SEL3=Vss might respectivelyreplace SEL0=Vss, SEL1=Vss, SEL2=Vss, and SEL3=Vcc in the set 230 ₁ ofvoltages SEL0 to SEL3 for memory block 210 ₁ in FIG. 5A, while theremaining memory blocks 240 ₂ to 240 ₄ are unselected. The voltagesSEL0=Vcc, SEL1=Vcc, SEL2=Vss, and SEL3=Vss might be applied to theselector word lines 315 _(D3), 315_(D4), 315_(D5), and 315 _(D6) ofmemory block 210 ₁, as programmed in FIG. 6, while the read voltage isapplied to selected word line 315 ₁ in block 210 ₁ and while the passvoltage is applied to unselected word lines 315 _(D1), 315_(D2),315_(D7), 315_(D8), and 315 ₂ to 315 _(N) in block 210 ₁, for example.

In the example of FIG. 6, the voltages of Vss and Vcc can activate allof the erased selector memory cells in memory block 210 ₁. The voltageSEL0=Vcc activates the programmed selector memory cells in the portion240 ₁ of the row of selector memory cells commonly coupled to word line315 _(D3) in memory block 210 ₁. The voltage SEL1=Vcc activates theprogrammed selector memory cells in the portion 240 ₂ of the row ofselector memory cells commonly coupled to word line 315 _(D4) in memoryblock 210 ₁. The voltage SEL2=Vss is insufficient to activate theprogrammed selector memory cells in portion 240 ₃ commonly coupled toselector word line 315 _(D5), and the voltage SEL3=Vss is insufficientto activate the programmed selector memory cells in portion 240 ₄commonly coupled to selector word line 315 _(D6). Therefore, theprogrammed selector memory cells in the portions 240 ₃ and 240 ₄ of therows of memory cells respectively commonly coupled to word lines 315_(D5) and 315 ₁)₆ in memory block 210 ₁ are deactivated. The programmedselector memory cells that are deactivated isolate the strings of memorycells in the portions 240 ₃ and 240 ₄ memory block 210 ₁ that includethose deactivated selector memory cells and thus prevent the data (e.g.,user data and ECC) stored in portions 240 ₃ and 240 ₄ from respectivelybeing output to (e.g., sensed at) portions 250 ₃ and 250 ₄ of pagebuffer 220. That is, the deactivated selector memory cells isolate thestrings of memory cells that include those deactivated selector memorycells from the bit lines that are coupled to the select transistors thatare coupled to the strings with the deactivated selector memory cells,while the select transistors are activated, for example.

In the example of FIG. 6, the only portions 240 of the rows of selectormemory cells that are activated are the portions 240 ₁ and 240 ₂ of therows of selector memory cells respectively commonly coupled to wordlines 315 _(D3) and 315 _(D4). As such, the only data that is sensed isfrom the strings of memory cells in portions 240 ₁ and 240 ₂ thatinclude the selector memory cells that are activated. For example, thedata from portions 240 ₁ and 240 ₂ may be respectively sensed atportions 250 ₁ and 250 ₂ of page buffer 220, e.g., concurrently.

FIG. 7 is a schematic diagram of a memory block 210 during the sensingof certain selected bit lines in memory block 210. Memory block 210might be a single selected memory block selected from a plurality ofmemory blocks, such as memory blocks 210 ₁ to 210 ₄ in FIG. 2. Commonnumbering is used in FIGS. 3 and 7 to denote similar (e.g., the same)components, e.g., where the commonly numbered components may be asdescribed above in conjunction with FIG. 3.

The selector memory cells 302 _(D5) and 302 _(D6) respectively commonlycoupled to selector word lines 315 _(D5) and 315 _(D6) that are enclosedin boxes might be programed and might have, for example, a logic levelzero, whereas the remaining selector memory cells 302 _(D5) and 302_(D6) respectively commonly coupled to selector word lines 315 _(D5) and315 _(D6) might be erased and might have, for example, a logic levelone. The programed and erased states of the selector memory cells 302_(D5) and 302 _(D6) that are respectively coupled to selector word lines315 _(D5) and 315 _(D6) in conjunction with the voltages SEL0 and SEL1respectively applied to selector word lines 315 _(D5) and 315 _(D6)facilitates the selection of strings 306 corresponding to certain bitlines (e.g., odd or even bit lines) 310 for sensing (e.g., reading). Forexample, this might be referred to as distributed sensing. The odd oreven selected bit lines 310 might be sensed concurrently, for example.

The voltages SEL0 and SEL1 might be respectively applied to selectorword lines 315 _(D5) and 315 _(D6) while a read voltage is applied toselected word line 315 ₁ in block 210 in FIG. 7, while the pass voltageis applied to unselected word lines 315 _(D1) to 315 _(D4), 315 _(D7),315_(D8), and 315 ₂ to 315 _(N) in block 210 in FIG. 7, and while anactivation voltage is applied to select line 312 that activates the row(e.g., all) of the select transistors 304 commonly coupled to selectline 312, for example.

The odd bit lines (e.g. bit lines 310 ₁, 310 ₃, 310 ₅, and 310 ₇), andthus the strings 306 corresponding to the odd bit lines, might beselected, without selecting the even bit lines (e.g. bit lines 310 ₂,310 ₄, 310 ₆, and 310 ₈), and thus the strings 306 corresponding to theeven bit lines, by activating the row of selector memory cells 302 _(D6)commonly coupled to selector word line 315 _(D6) while the selectormemory cells 302 _(D5) commonly coupled to selector word line 315 _(D5)that are in strings 306 corresponding to even bit lines are deactivatedand the selector memory cells 302 _(D5) commonly coupled to selectorword line 315 _(D5) that are in strings 306 corresponding to odd bitlines are activated.

For example, to select the odd bit lines, and thus the strings 306corresponding to the odd bit lines, without selecting the even bitlines, and thus the strings 306 corresponding to the even bit lines, thevoltage SEL0 might be a voltage, such as Vss, that is below thethreshold voltages of the programmed (e.g., the boxed) memory cells 302_(D5) and above the threshold voltages of the erased (e.g., the unboxed)memory cells 302 _(D5), whereas the voltage SEL1 might be a voltage,such as Vcc, that is above the threshold voltages of the programmedmemory cells 302 _(D6) and above the threshold voltages of the erasedmemory cells 302 _(D6).

The voltage SEL1=Vcc activates the entire row of selector memory cells302 _(D6) (e.g., the programmed and erased memory cells 302 _(D6))commonly coupled to selector word line 315 _(D6). The voltage SEL0=Vssactivates the erased selector memory cells 302 _(D5) commonly coupled toselector word line 315 _(D5), but is insufficient to activate theselector memory cells 302 _(D5) commonly coupled to selector word line315 _(D5) that are programmed (e.g., the boxed selector memory cells 302_(D5)). For example, the programmed selector memory cells 302 _(D5) aredeactivated, whereas the programmed selector memory cells 302 _(D6) areactivated. Therefore, the strings 306, corresponding to even bit lines310 that contain programmed selector memory cells 302 _(D5) that aredeactivated are isolated from their corresponding even bit lines 310,and thus unselected. That is, the programmed selector memory cells 302_(D5) that are deactivated isolate the strings that include thoseprogrammed selector memory cells 302 _(D5) that are deactivated from theeven bit lines 310, while the select transistors 304 coupled to thosestrings and the even bit lines are activated, for example. The strings306, corresponding to odd bit lines 310, that contain programmedselector memory cells 302 _(D6) that are activated and erased selectormemory cells 302 _(D5) that are activated are activated, and thus areselected, and are thus coupled to the corresponding odd bit lines 310.

The even bit lines (e.g. bit lines 310 ₂, 310 ₄, 310 ₆, and 310 ₈), andthus the strings 306 corresponding to the even bit lines might beselected, without selecting the odd bit lines (e.g. bit lines 310 ₁, 310₃, 310 ₅, and 310 ₇), and thus the strings 306 corresponding to even bitlines, by activating the row of selector memory cells 302 _(D5) commonlycoupled to selector word line 315 _(D5), while the selector memory cells302 _(D6) commonly coupled to selector word line 315 _(D6) that are instrings 306 corresponding to odd bit lines are deactivated and theselector memory cells 302 _(D6) commonly coupled to selector word line315 _(D6) that are in strings 306 corresponding to even bit lines areactivated.

For example, to select the even bit lines, and thus the strings 306corresponding to the even bit lines, without selecting the odd bitlines, and thus the strings 306 corresponding to the odd bit lines, thevoltage SEL0 might be Vcc, and the voltage SEL1 might be Vss. Thevoltage SEL0=Vcc activates the entire row of selector memory cells 302_(D5) (e.g., the programmed and erased memory cells 302 _(D5)) commonlycoupled to selector word line 315 _(D5). The voltage SEL1=Vss activatesthe erased selector memory cells 302 _(D6) commonly coupled to selectorword line 315 _(D6), but is insufficient to activate the selector memorycells 302 _(D6) commonly coupled to selector word line 315 _(D6) thatare programmed (e.g., the boxed selector memory cells 302 _(D6)). Forexample, the programmed selector memory cells 302 _(D6) are deactivated,whereas the programmed selector memory cells 302 _(D5) are activated.Therefore, the strings 306, corresponding to odd bit lines 310, thatcontain programmed selector memory cells 302 _(D6) that are deactivatedare isolated from their corresponding odd bit lines 310, and thus areunselected, whereas the strings 306, corresponding to even bit lines310, that contain programmed selector memory cells 302 _(D5) that areactivated and erased selector memory cells 302 _(D6) that are activatedare activated, and thus are selected.

FIG. 8 is a schematic diagram of a memory block 210 during the sensingof certain selected (e.g., odd or even) bit lines in a certain selectedportion of memory block 210. Therefore, the example in FIG. 8 is anotherexample of distributed sensing, where the strings 306 corresponding toodd or even bit lines in a selected portion of memory block 210 areselected for sensing.

Memory block 210 might be a single selected memory block selected from aplurality of memory blocks, such as memory blocks 210 ₁ to 210 ₄ in FIG.2. Common numbering is used in FIGS. 3 and 8 to denote similar (e.g.,the same) components, e.g., where the commonly numbered components maybe as described above in conjunction with FIG. 3.

A portion 840 ₁ of the memory array 210 in the example of FIG. 8 mightinclude the strings 306 respectively corresponding to bit lines 310 ₁ to310 ₄, and a portion 840 ₂ of the memory array 210 might include thestrings 306 respectively corresponding to bit lines 310 ₅ to 310 ₈, forexample. The odd or even bit lines 310, and thus the strings 306corresponding to the odd or even bit lines 310, in portion 840 ₁ orportion 840 ₂ might be selected by selecting the odd or even bit linesfor the entire block 210 and then selecting either portion 840 ₁ orportion 840 ₂. The odd or even selected bit lines 310 in a selectedportion 840 might be sensed concurrently, for example.

The selector memory cells 302 _(D7) and 302 _(D8) respectively commonlycoupled to selector word lines 315 _(D7) and 315 _(D8) that are enclosedin boxes might be programed and might have, for example, a logic levelzero, whereas the remaining selector memory cells 302 _(D7) and 302_(D8) respectively commonly coupled to selector word lines 315 _(D7) and315 _(D8) might be erased and might have, for example, a logic levelone. The selector memory cells 302 _(D6) that are enclosed in box 810 ₁,that are commonly coupled to selector word line 315 _(D6), and that arein strings 306 respectively corresponding to bit lines 310 ₁ to 310 ₄might be programed and might have, for example, a logic level zero,whereas the remaining selector memory cells 302 _(D6) that are commonlycoupled to selector word line 315 _(D6) and that are in strings 306respectively corresponding to bit lines 310 ₅ to 310 ₈ might be erasedand might have a logic level one. The selector memory cells 302 _(D5)that are enclosed in box 810 ₂, that are commonly coupled to selectorword line 315 _(D5), and that are in strings 306 respectivelycorresponding to bit lines 310 ₅ to 310 ₈ might be programed and mighthave, for example, a logic level zero, whereas the remaining selectormemory cells 302 _(D5) that are commonly coupled to selector word line315 _(D5) and that are in strings 306 respectively corresponding to bitlines 310 ₁ to 310 ₄ might be erased and might have a logic level one.

The programed and erased states of the selector memory cells 302 _(D6)that are commonly coupled to selector word line 315 _(D6) and theprogramed and erased states of the selector memory cells 302 _(D5) thatare commonly coupled to selector word line 315 _(D5) in conjunction withthe voltages SEL1 and SEL0 respectively applied to selector word lines315 _(D6) and 315 _(D5) facilitates the selection of the portions 840 ₁and 840 ₂ for sensing (e.g., reading). The programed and erased statesof the selector memory cells 302 _(D7) and 302 _(D8) that arerespectively coupled to selector word lines 315 _(D7) and 315 _(D8) inconjunction with the voltages SEL2 and SEL3 respectively applied toselector word lines 315 _(D7) and 315 _(D8) facilitates the selection ofstrings 306 corresponding to certain bit lines (e.g., odd or even bitlines) 310 for sensing (e.g., reading) in one of the portions 840 ₁ or840 ₂ when that portion is selected. The voltages SEL1 and SEL0 might berespectively applied to selector word lines 315 _(D6) and 315 _(D5), andthe voltages SEL2 and SEL3 might be respectively applied to selectorword lines 315 _(D7) and 315 _(D8) while a read voltage is applied toselected word line 315 ₁ in block 210 in FIG. 8, while the pass voltageis applied to unselected word lines 315 _(D1) to 315 _(D4), and 315 ₂ to315 _(N) in block 210 in FIG. 8, and while an activation voltage isapplied to select line 312 that activates the row (e.g., all) of theselect transistors 304 commonly coupled to select line 312, for example.

To select portion 840 ₁ without selecting portion 840 ₂, the row ofselector memory cells 302 _(D6) commonly coupled to selector word line315 _(D6) is activated, while the selector memory cells 302 _(D5) instrings 306 in portion 840 ₁ (e.g., corresponding to bit lines 310 ₁ to310 ₄) that are commonly coupled to selector word line 315 _(D5) areactivated and the selector memory cells 302 _(D5) in strings 306 inportion 840 ₂ (e.g., corresponding to bit lines 310 ₅ to 310 ₈) that arecommonly coupled to selector word line 315 _(D5) are deactivated.

For example, to select portion 840 ₁ without selecting portion 840 ₂,the voltage SEL0 might be a voltage, such as Vss, that is below thethreshold voltages of the programmed selector memory cells 302 _(D5) inbox 810 ₂ and above the threshold voltages of the erased (e.g., theunboxed) memory cells 302 _(D5), whereas the voltage SEL1 might be avoltage, such as Vcc, that is above the threshold voltages of theprogrammed memory cells 302 _(D6) in box 810 ₁ and above the thresholdvoltages of the erased (e.g., the unboxed) memory cells 302 _(D6). Thevoltage SEL1=Vcc activates the entire row of selector memory cells 302₁)₆ (e.g., the programmed and erased memory cells 302 _(D6)) commonlycoupled to selector word line 315 ₁₆. The voltage SEL0=Vss activates theerased selector memory cells 302 _(D5) commonly coupled to selector wordline 315 _(D5), but is insufficient to activate the selector memorycells 302 _(D5) commonly coupled to selector word line 315 _(D5) thatare programmed (e.g., the selector memory cells 302 _(D5) in box 810 ₂).For example, the programmed selector memory cells 302 _(D5) aredeactivated, whereas the programmed selector memory cells 302 _(D6) areactivated. As such, the strings 306 in portion 840 ₂ are isolated fromtheir respective bit lines, and portion 840 ₂ is not selected, whileportion 840 ₁ is selected since the memory cells 302 _(D6) commonlycoupled to selector word line 315 ₁)₆ (e.g., the selector memory cells302 _(D6) in box 810 ₁) are activated and since the erased memory cells302 _(D5) in portion 840 ₁ commonly coupled to selector word line 315_(D5) (e.g., the unboxed memory cells 302 _(D5)) are activated. Notethat the programmed selector memory cells 302 _(D5) that are deactivatedrespectively isolate the strings 306 that include the selector memorycells 302 _(D5) that are deactivated corresponding to bit lines 310 ₅ to310 ₈ from bit lines 310 ₅ to 310 ₈ while the select transistors coupledbetween those strings 306 and bit lines 310 ₅ to 310 ₈ are activated.

To select portion 840 ₂ without selecting portion 840 ₁, the row ofselector memory cells 302 _(D5) commonly coupled to selector word line315 _(D5) is activated, while the selector memory cells 302 _(D6) instrings 306 in portion 840 ₂ (e.g., corresponding to bit lines 310 ₅ to310 ₈) that are commonly coupled to selector word line 315 _(D6) areactivated and the selector memory cells 302 _(D6) in strings 306 inportion 840 ₁ (e.g., coupled bit lines 310 ₁ to 310 ₄) that are commonlycoupled to selector word line 315 _(D6) are deactivated.

For example, to select portion 840 ₂ without selecting portion 840 ₁,the voltage SEL1 might be a voltage, such as Vss, that is below thethreshold voltages of the programmed memory cells 302 _(D6) in box 810 ₁and above the threshold voltages of the erased (e.g., the unboxed)memory cells 302 ₁₃₆, whereas the voltage SEL0 might be a voltage, suchas Vcc, that is above the threshold voltages of the programmed memorycells 302 _(D5) in box 810 ₂ and above the threshold voltages of theerased (e.g., the unboxed) memory cells 302 _(D5). The voltage SEL0=Vccactivates the entire row of selector memory cells 302 _(D5) (e.g., theprogrammed and erased memory cells 302 _(D5)) commonly coupled toselector word line 315 _(D5). The voltage SEL1=Vss activates the erasedselector memory cells 302 _(D6) commonly coupled to selector word line315 _(D6), but is insufficient to activate the selector memory cells 302_(D6) commonly coupled to selector word line 315 _(D6) that areprogrammed (e.g., the selector memory cells 302 _(D6) in box 810 ₁). Forexample, the programmed selector memory cells 302 _(D6) are deactivated,whereas the programmed selector memory cells 302 _(D5) are activated. Assuch, the strings 306 in portion 840 ₁ are isolated for their respectivebit lines and portion 840 ₁ portion is not selected, while portion 840 ₂is selected since the memory cells 302 _(D5) in portion 840 ₂ commonlycoupled to selector word line 315 _(D5) (e.g., the selector memory cells302 _(D5) in box 810 ₂) are activated and since the erased memory cells302 _(D6) in portion 840 ₂ commonly coupled to selector word line 315_(D6) (e.g., the unboxed memory cells 302 _(D6)) are activated.

The odd bit lines (e.g., bit lines 310 ₁, 310 ₃, 310 ₅, and 310 ₇), andthus the strings 306 corresponding to the odd bit lines, might beselected, without selecting the even bit lines (e.g., bit lines 310 ₂,310 ₄, 310 ₆, and 310 ₈), and thus the strings 306 corresponding to theeven bit lines, by activating the row of selector memory cells 302 _(D8)commonly coupled to selector word line 315 _(D8), while the selectormemory cells 302 _(D7) commonly coupled to selector word line 315 _(D7)that are in strings 306 corresponding to even bit lines are deactivatedand the selector memory cells 302 _(D7) commonly coupled to selectorword line 315 _(D7) that are in strings 306 corresponding to odd bitlines are activated. With the odd bit lines (e.g., bit lines 310 ₁, 310₃, 310 ₅, and 310 ₇) thus selected, the odd bit lines (e.g., bit lines310 ₁ and 310 ₃) corresponding to strings 306 in portion 840 ₁ might beselected by selecting portion 840 ₁, or the odd bit lines (e.g., bitlines 310 ₅ and 310 ₇) corresponding to strings 306 in portion 840 ₂might be selected by selecting portion 840 ₂.

For example, to select the odd bit lines, and thus the strings 306corresponding to the odd bit lines, without selecting the even bitlines, and thus the strings 306 corresponding to the even bit lines, thevoltage SEL2 might be a voltage, such as Vss, that is below thethreshold voltages of the programmed (e.g., the boxed) memory cells 302_(D7) and above the threshold voltages of the erased (e.g., the unboxed)memory cells 302 _(D7), whereas the voltage SEL3 might be a voltage,such as Vcc, that is above the threshold voltages of the programmedmemory cells and 302 _(D8) and above the threshold voltages of theerased memory cells 302 _(D8). The voltage SEL3=Vcc activates the entirerow of selector memory cells 302 _(D8) (e.g., the programmed and erasedmemory cells 302 _(D8)) commonly coupled to selector word line 315_(D8). The voltage SEL2=Vss activates the erased selector memory cells302 _(D7) commonly coupled to selector word line 315 _(D7), but isinsufficient to activate the selector memory cells 302 _(D7) commonlycoupled to selector word line 315 _(D7) that are programmed (e.g., theboxed selector memory cells 302 _(D7)). Therefore, the strings 306,corresponding to even bit lines 310, that contain programmed selectormemory cells 302 _(D7) that are deactivated are isolated from theircorresponding even bit lines 310, and thus are unselected, whereas thestrings 306, corresponding to odd bit lines 310, that contain programmedselector memory cells 302 _(D8) that are activated and erased selectormemory cells 302 _(D7) that are activated are activated, and thus areselected.

The even bit lines (e.g., bit lines 310 ₂, 310 ₄, 310 ₆, and 310 ₈), andthus the strings 306 corresponding to the even bit lines, might beselected, without selecting the odd bit lines (e.g., bit lines 310 ₁,310 ₃, 310 ₅, and 310 ₇), and thus the strings 306 corresponding to theodd bit lines, by activating the row of selector memory cells 302 _(D7)commonly coupled to selector word line 315 _(D7), while the selectormemory cells 302 _(D8) commonly coupled to selector word line 315 _(D8)that are in strings 306 coupled to odd bit lines are deactivated and theselector memory cells 302 _(D8) commonly coupled to selector word line315 _(D8) that are in strings 306 coupled to even bit lines areactivated. With the even bit lines (e.g., bit lines 310 ₂, 310 ₄, 310 ₆,and 310 ₈) thus selected, the even bit lines (e.g., bit lines 310 ₂ and310 ₄) corresponding to strings 306 in portion 840 ₁ might be selectedby selecting portion 840 ₁, or the even bit lines (e.g., bit lines 310 ₆and 310 ₈) corresponding to strings 306 in portion 840 ₂ might beselected by selecting portion 840 ₂.

For example, to select the even bit lines, and thus the strings 306corresponding to the even bit lines, without selecting the odd bitlines, and thus the strings 306 corresponding to the odd bit lines, thevoltage SEL2 might be Vcc, and the voltage SEL3 might be Vss. Thevoltage SEL2=Vcc activates the entire row of selector memory cells 302_(D7) (e.g., the programmed and erased memory cells 302 _(D7)) commonlycoupled to selector word line 315 _(D7). The voltage SEL3=Vss activatesthe erased selector memory cells 302 _(D8) commonly coupled to selectorword line 315 _(D8), but is insufficient to activate the selector memorycells 302 _(D8) commonly coupled to selector word line 315 _(D8) thatare programmed (e.g., the boxed selector memory cells 302 _(D8)).Therefore, the strings 306, corresponding to odd bit lines 310, thatcontain programmed selector memory cells 302 _(D8) that are deactivatedare isolated from their corresponding odd bit lines 310, and thus areunselected, whereas the strings 306, corresponding to even bit lines310, that contain programmed selector memory cells 302 _(D7) that areactivated and erased selector memory cells 302 _(D8) that are activatedare activated, and thus are selected.

In the examples discussed above in conjunction with FIGS. 3-5, data froma portion 240 of a block might be output to (e.g., sensed by) arespective one of portions 250 of page buffer 220. For example, data(e.g., four kilobytes of user data plus the ECC for that data) fromportion 240 ₁ of memory block 210 ₄, portion 240 ₂ of memory block 210₂, portion 240 ₃ of memory block 210 ₃, and portion 240 ₄ of memoryblock 210 ₁ might be respectively output to (e.g., sensed by) portions250 ₁, 250 ₂, 250 ₃, and 250 ₄ of page buffer 220. However, for someembodiments, data (e.g., one kilobyte of user data plus the ECC for thatdata) from a portion of each of a plurality blocks might be output toone portion 250 (e.g., portion 250 ₁) of page buffer 220, data (e.g.,one kilobyte of user data plus the ECC for that data) from anotherportion of each of the plurality blocks might be output to anotherportion 250 (e.g., portion 250 ₂) of page buffer 220, etc. That is,instead of each portion 250 of page buffer 220 having data from the samememory block, each portion 250 of page buffer 220 might have data fromportions of different blocks, for example. This can be illustrated bythe example of FIG. 9.

In the example of FIG. 9, the memory blocks 210 _(i) and 210 _(j) mightbe as described above in conjunction with the example of FIG. 3 or ofFIG. 4, e.g., memory blocks 210 _(i) and 210 _(j) might form a portionof memory array 200 in FIG. 2. In FIG. 9, each of the portions 240 ₁ to240 ₄ of memory blocks 210 _(i) and 210 _(j) might have a plurality ofsub-portions, such as sub-portions 940 ₁ to 940 ₄. Note that theselector memory cells in the sub-portions 940 of each portion 240 inFIG. 9 might be programmed (e.g., assigned all logic zeros) or erased(e.g., assigned all logic ones).

Each of the portions 250 ₁ to 250 ₄ of page buffer 220 might have aplurality of sub-portions 950, such as sub-portions 950 ₁ to 950 ₄. Forexample, sub-portions 950 ₁ to 950 ₄ in portion 250 ₁ might respectivelycorrespond to sub-portions 940 ₁ to 940 ₄ in portion 240 ₁; sub-portions950 ₁ to 950 ₄ in portion 250 ₂ might respectively correspond tosub-portions 940 ₁ to 940 ₄ in portion 240 ₂; etc. Each portion 250might sense four kilobytes of user data plus ECC, for example, whileeach sub-portion 950 might sense one kilobyte of user data plus ECC, forexample.

Sets 230 _(i) and 230 _(j) of voltages SEL0 to SEL3 might berespectively applied to the selector word lines of memory blocks 210_(i) and 210 _(j) while a read voltage is applied to a selected wordline (e.g., selected word line 315 ₁) in each of memory blocks 210 _(i)and 210 _(j) and a pass voltage is applied to unselected word lines(e.g., unselected word lines 315 _(D1), 315_(D2), 315_(D7), 315_(D8),and 315 ₂ to 315 _(N)) in each of memory blocks 210 _(i) and 210 _(j).For example, applying set 230 _(i) to the selector word lines coupled tothe selector memory cells of memory block 210 _(i) allows data fromsub-portion 940 ₂ of portions 240 ₁ to 240 ₄ of block 210 _(i) to berespectively sensed by sub-portion 950 ₂ of portions 250 ₁ to 250 ₄ ofpage buffer 220, and applying set 230 _(j) to the selector word linescoupled to the selector memory cells of memory block 210 _(j) allowsdata from sub-portion 940 ₁ of portions 240 ₁ to 240 ₄ of block 210 _(j)to be respectively sensed by sub-portion 950 ₁ of portions 250 ₁ to 250₄ of page buffer 220.

The sub-portions 940 ₂ of each of the portions 240 of block 210 _(i)might have the same page address, and the sub-portions 940 ₁ of each ofthe portions 240 of block 210 _(j) might have the same page address. Forexample, sub-portions 940 ₂ of each of the portions 240 of block 210_(i) might have the same page address as the sub-portions 940 ₁ of eachof the portions 240 of block 210 _(j) so that the data from thesub-portions 940 ₂ of each of the portions 240 of block 210 _(i) and thedata from the sub-portions 940 ₁ of each of the portions 240 of block210 _(j) is sensed concurrently at the portions 250 of page buffer 220.That is, the data in sub-portions 950 ₁ of portions 250 of page buffer220 and the data in sub-portions 950 ₂ of portions 250 of page buffer220 may sensed concurrently, for example, in response to a senseamplifier enable signal commonly received at sub-portions 950 ₁ andsub-portions 950 ₂.

Alternatively, for example, sub-portions 940 ₂ of each of the portions240 of block 210 _(i) might have a different page address than thesub-portions 940 ₁ of each of the portions 240 of block 210 _(j), sothat the data from the sub-portions 940 ₂ of each of the portions 240 ofblock 210 _(i) are sensed concurrently at the portions 250 of pagebuffer 220 at a first time and the data from the sub-portions 940 ₁ ofeach of the portions 240 of block 210 _(j) are sensed concurrently atthe portions 250 of page buffer 220 at a second time different than thefirst time. That is, the data in sub-portions 950 ₁ of portions 250 ofpage buffer 220 might be sensed concurrently in response to a senseamplifier enable signal commonly received at sub-portions 950 ₁, forexample, and the data in sub-portions 950 ₂ of portions 250 of pagebuffer 220 might be sensed concurrently in response to a different senseamplifier enable signal commonly received at sub-portions 950 ₂, forexample.

FIG. 10 is a block diagram illustrating a memory array 200, during aprogramming operation. Each of the memory blocks 210 ₁ to 210 ₄ may beas described above in conjunction with FIG. 3 or FIG. 4. The selectormemory cells in memory blocks 210 ₁ to 210 ₄ might be programmed asshown in FIG. 5A, for example. The sets 230 ₁ to 230 ₄ of voltages SEL0to SEL3 from FIG. 5A might be respectively applied to the selector wordlines, and thus the selector memory cells, of memory blocks 210 ₁ to 210₄. For example, voltages SEL0 to SEL3 might be respectively applied tothe selector word lines 315 _(D3) to 315 _(D6) in each block 210, asshown in FIG. 5A. As such, the states of the memory cells, in responseto applying the sets 230 ₁ to 230 ₄ of voltages SEL0 to SEL3 to theselector word lines, might be as shown in FIG. 5A, where all of theerased selector memory cells (e.g., having logic level one in FIG. 5A)are activated (e.g., conducting).

During a programming operation, with reference to FIG. 3 or 4, one ofthe word lines 315 ₁ to 315 _(N), e.g., word line 315 ₁, in each of thememory blocks 210 might be selected for programming, for example, whilethe remaining word lines 315 _(D1), 315_(D2), 315_(D7), 315_(D8), and315 ₂ to 315 _(N) in each of the memory blocks 210 might be unselected.Memory cells 302 ₁ (e.g., one or more memory cells 302 ₁) in portions240 ₄, 240 ₂, 240 ₃, and 240 ₁ respectively in blocks 210 ₁, 210 ₂, 210₃, and 210 ₄ and commonly coupled to selected word lines 315 ₁ might betarget memory cells targeted for programming. As such, the portions 240₄, 240 ₂, 240 ₃, and 240 ₁ respectively in blocks 210 ₁, 210 ₂, 210 ₃,and 210 ₄ might be referred to as selected portions, e.g., that might beselected concurrently. The remaining portions 240 in each of the blocks210, e.g., portions 240 ₁ to 240 ₃ in block 210 ₁, portions 240 ₁, 240₃, and 240 ₄ in block 210 ₂, portions 240 ₁, 240 ₂, and 240 ₄ in block210 ₃, and portions 240 ₂ to 240 ₄ in block 210 ₄, might be unselectedportions. Therefore, the remaining memory cells 302 ₁ commonly coupledto the selected word line 315 ₁ in the unselected portions of each block210 are untargeted memory cells 302 ₁ not targeted for programming.

The selector memory cells in selected portions 240 ₄, 240 ₂, 240 ₃, and240 ₁ respectively in blocks 210 ₁, 210 ₂, 210 ₃, and 210 ₄ that areprogramed (e.g., are assigned logic level zero in FIG. 5A) and areactivated in response to the selector memory cells in blocks 210 ₁, 210₂, 210 ₃, and 210 ₄ respectively receiving sets 230 ₁, 230 ₂, 230 ₃, and230 ₄. This selects portions 240 ₄, 240 ₂, 240 ₃, and 240 ₁ respectivelyin blocks 210 ₁, 210 ₂, 210 ₃, and 210 ₄, in that the erased selectormemory cells in selected portions 240 ₄, 240 ₂, 240 ₃, and 240 ₁respectively in blocks 210 ₁, 210 ₂, 210 ₃, and 210 ₄ are also activatedin response to the selector memory cells in blocks 210 ₁, 210 ₂, 210 ₃,and 210 ₄ respectively receiving sets 230 ₁, 230 ₂, 230 ₃, and 230 ₄.The selector memory cells in the unselected portions in each of blocks210 are also programed (e.g., are assigned logic level zero), but remaindeactivated (non-conducting) in response to those selector memory cellsin blocks 210 ₁, 210 ₂, 210 ₃, and 210 ₄ respectively receiving sets 230₁, 230 ₂, 230 ₃, and 230 ₄.

Applying the sets 230 ₁ to 230 ₄ respectively to the selector memorycells in blocks 210 ₁ to 210 ₄ as programmed in FIG. 5A, selects theportions 240 ₄, 240 ₂, 240 ₃, and 240 ₁ respectively of blocks 210 ₁,210 ₂, 210 ₃, and 210 ₄ for programming while leaving the remainingportions in each of blocks 210 ₁, 210 ₂, 210 ₃, and 210 ₄ unselected forprogramming. For example, the sets 230 ₁ to 230 ₄ might be respectivelyapplied to the selector word lines in blocks 210 ₁ to 210 ₄, e.g.,concurrently while a program pass voltage is applied to the unselectedword lines 315 _(D1), 315_(D2), 315_(D7), 315_(D8), and 315 ₂ to 315_(N) in blocks 210 ₁ to 210 ₄, e.g., concurrently, while a voltage, suchas Vss, is applied to bit lines 310 (FIG. 3 or 4), e.g., concurrently,and while the row of select transistors 304, commonly coupled to selectline 312 and respectively coupled between the bit lines 310 and thestrings 306 in each of blocks 210 ₁ to 210 ₄, is activated, e.g.,concurrently in blocks 210 ₁ to 210 ₄, e.g., in response to a voltage,such as Vcc, being applied to each select line 312.

A program voltage might be applied to the selected word line 315 ₁ ineach of blocks 210 while the sets 230 ₁ to 230 ₄ are respectively to theselector memory cells in blocks 210 ₁ to 210 ₄, e.g., concurrently,while the program pass voltage is applied to the unselected word lines315 _(D1), 315 _(D2), 315 _(D7), 315_(D8), and 315 ₂ to 315 _(N) in eachof blocks 210, while the select transistors 304 are activated, and whilethe voltage Vss is applied to bit lines 310. Note that in the event thatsome of the target memory cells 302 ₁ program before others, an inhibitvoltage, such as Vcc, might be applied to the bit lines 310 coupled tothe stings 306 containing those memory cells.

The programmed selector memory cells that are activated (e.g.,conducting) in each of the blocks 210 in FIG. 5A allow the strings 306(FIGS. 3 and 4) of memory cells that include an activated selectormemory cell and a target memory cell to conduct and to be coupled to thebit lines 310 by the activated select transistors 304. For example, thestrings 306 of memory cells in portion 240 ₄ of memory block 210 ₁, thestrings 306 of memory cells in portion 240 ₂ of memory block 210 ₂, thestrings 306 of memory cells in portion 240 ₃ of memory block 210 ₃, andthe strings 306 of memory cells in portion 240 ₁ of memory block 210 ₄are activated.

An activated programmed selector memory cell and an activated selecttransistor 304 couple a bit line 310 to a channel of a target memorycell 302 ₁ in the string 306 with the activated selector memory cell(e.g., to a channel of the string 306 that includes the target memorycell 302 ₁ and the activated selector memory cell) and act to maintainthe channel at about the voltage, e.g., Vss, of the bit line 310,thereby preventing the pass voltage applied to unselected word lines 315_(D1), 315 _(D2), 315 _(D7), 315 _(D8), and 315 ₂ to 315 _(N) and theprogram voltage applied to selected word line 315 ₁ from increasing(e.g., boosting) the voltage of the channel. As such, the differencebetween the program voltage applied to selected word line 315 ₁ and thevoltage on channel, and thus the voltage difference across thecharge-storage structure 334 (FIG. 3) of the target memory cell 302 ₁,is sufficient to produce a change in the threshold (Vt) level of thetarget memory cell 302 ₁.

The deactivated programmed selector memory cells in each of the blocks210 in FIG. 5A electrically isolate the strings 306 (FIGS. 3 and 4) thatinclude those deactivated selector memory cells from the bit lines 310coupled to the activated select transistors 304 and those strings 306.For example, the strings 306 of memory cells in portions 240 ₁, 240 ₂,and 240 ₃ of memory block 210 ₁ are electrically isolated from the bitlines 310 that are coupled to the activated select transistors 304 inmemory block 210 ₁ that are coupled to the strings 306 of memory cellsin portions 240 ₁, 240 ₂, and 240 ₃ of memory block 210 ₁; the strings306 of memory cells in portions 240 ₁, 240 ₃, and 240 ₄ of memory block210 ₂ are electrically isolated from the bit lines 310 that are coupledto the activated select transistors 304 in memory block 210 ₂ that arecoupled to the strings 306 of memory cells in portions 240 ₁, 240 ₃, and240 ₄ of memory block 210 ₂; the strings 306 of memory cells in portions240 ₁, 240 ₂, and 240 ₄ of memory block 210 ₃ are electrically isolatedfrom the bit lines 310 that are coupled to the activated selecttransistors 304 in memory block 210 ₃ that are coupled to the strings306 of memory cells in portions 240 ₁, 240 ₂, and 240 ₄ of memory block210 ₃; and the strings 306 of memory cells in portions 240 ₂, 240 ₃, and240 ₄ of memory block 210 ₄ are electrically isolated from the bit lines310 that are coupled to the activated select transistors 304 in memoryblock 210 ₄ that are coupled to the strings 306 of memory cells inportions 240 ₂, 240 ₃, and 240 ₄ of memory block 210 ₄.

A deactivated programmed selector memory cell prevents a voltage (e.g.,a boosted voltage) on the channel of the memory cells in a string 306,including the deactivated selector memory cell and an untargeted memorycell 302 ₁ coupled to the selected word line 315 ₁, from dischargingthrough an activated select transistor 304 coupled to a bit line 310,e.g., at the voltage Vss, coupled to the select transistor 304. That is,the voltage of channel might be boosted by pre-charge operations and bythe pass voltage applied to unselected word lines 315 _(D1), 315_(D2),315_(D7), 315_(D8), and 315 ₂ to 315 _(N) and the program voltageapplied to selected word line 315 ₁, for example. As such, thedifference between the program voltage applied to selected word line 315₁ and the voltage on channel of the untargeted memory cell 302 ₁, andthus the voltage difference across the charge-storage structure 334 ofthe untargeted memory cell 302 ₁ coupled to the selected word line 315₁, is insufficient to produce a change in the Vt level of the untargetedmemory cell 302 ₁ coupled to the selected word line 315 ₁. That is, theVt of the untargeted memory cell 302 ₁ is inhibited from being changedby the program voltage.

A deactivated programmed selector memory cell allows an untargetedmemory cell included in the same string in an unselected portion of ablock to be inhibited while the Vt of a targeted memory cell in anotherstring, including an activated selector memory cell, in a selectedportion of another block is shifted, where the untargeted and targetedmemory cells are coupled to different selected word lines that receivethe program voltage and where the string that includes the untargetedmemory cell and the string that includes the targeted memory cell areboth coupled by activated select gates to the same bit line that is at avoltage, such as Vss, sufficient to allow the Vt of the target memorycell to shift when the selected word line coupled to the target memorycell is at the program voltage. For example, the inhibiting of anuntargeted memory cell in a string may be controlled by the state of aselector memory cells in the same string and the voltage of the channelof the untargeted memory cell when a program voltage is applied to aselected word line coupled to the untargeted memory cell, and may beindependent of the voltage of a bit line coupled to the string by anactivated select gate while the program voltage is applied to theselected word line.

FIG. 11 presents a timing diagram for an example where portion 240 ₁ ofblock 210 ₄ and portion 240 ₂ of block 210 ₂ are programmedconcurrently. Voltages 1100 ₁ and 1100 ₂ are respectively applied to thebit lines coupled to portions 250 ₁ and 250 ₂ of page buffer 220 in FIG.10. Voltages 1105 ₁ and 1105 ₂ are respectively applied to unselectedword lines (e.g., unselected word lines 315 _(D1), 315_(D2), 315_(m),315 _(D8), and 315 ₂ to 315 _(N), FIGS. 3 and 4) of blocks 210 ₄ and 210₂. Voltages 1110 ₁ and 1110 ₂ are respectively applied to selected wordlines (e.g., selected word line 315 ₁, FIGS. 3 and 4) of blocks 210 ₄and 210 ₂. Voltages 1115 ₁ and 1115 ₂ are respectively applied to selectlines 312 (e.g., the drain select lines) of blocks 210 ₄ and 210 ₂.Voltages 1120 ₁ and 1120 ₂ are respectively applied to select lines 313(e.g., the source select lines) of blocks 210 ₄ and 210 ₂. The voltages1120 may be maintained at a voltage level, such as Vss, that isinsufficient to activate the select transistors 303 (e.g., the sourceselect transistors) coupled select lines 313 during the programmingoperation. Voltages 1125 ₁ and 1125 ₂ are respectively applied to theselector word lines 315 _(D3), 315_(D4), 315_(D5), and 315 _(D6) ofmemory blocks 210 ₄ and 210 ₂ (FIGS. 3, 4, and 5).

The voltages 1100 applied to the bit lines are initially at a voltagelevel, such as voltage level Vcc, sufficient to inhibit programming.While the voltages 1100 of the bit lines are at Vcc, the voltages 1115applied to the drain select lines, the voltages 1105 applied to theunselected word lines, the voltages 1110 applied to the selected wordlines, and the voltages 1125 applied to the selector word lines areincreased from a voltage level, such as Vss, e.g., to a voltage levelgreater than Vcc, such as Vcc+. This acts to pre-charge the channels ofthe strings of memory cells in portion 240 ₁ of block 210 ₄,corresponding to the bit lines coupled to portion 250 ₁ of page buffer220, and to pre-charge the channels of the strings of memory cells inportion 240 ₂ of block 210 ₂, corresponding to the bit lines coupled toportion 250 ₂ of page buffer 220. Note that the voltages SEL0, SEL1,SEL2, and, SEL3 respectively applied to the selector word lines 315_(D3), 315_(E4), 315_(D5), and 315 _(D6) (FIG. 5A) of memory blocks 210₄ and 210 ₂ are now at Vcc+.

Subsequently, while the voltages 1100 of the bit lines are at Vcc, thevoltages 1115 applied to the drain select lines are decreased from Vcc+to Vss, deactivating the drain select transistors coupled thereto, andthe voltages 1105 applied to the unselected word lines, the voltages1110 applied to the selected word lines, and the voltages 1125 appliedto the selector word lines are decreased from Vcc+ to Vss. After this,the voltages 1100 applied to bit lines that correspond to strings ofmemory cells in portion 240 ₁ of block 210 ₄ and in portion 240 ₂ ofblock 210 ₂, having memory cells that are targeted for programmingcoupled to selected word lines, are decreased from Vcc to a voltagelevel, such as Vss. However, the voltages 1100 applied to bit lines thatcorrespond to strings of memory cells in portion 240 ₁ of block 210 ₄and in portion 240 ₂ of block 210 ₂, having memory cells that are nottargeted for programming coupled to selected word lines, remain at Vcc,so that the memory cells coupled to selected word lines that are nottargeted for programming are inhibited from being programed.

While the voltages applied to the bit lines that correspond to stringsof memory cells having memory cells that are targeted for programmingare at Vss, the voltages 1115 applied to the drain select lines areincreased from Vss to Vcc, activating the drain select transistorscoupled thereto, and the voltages 1105 applied to the unselected wordlines and the voltages 1110 applied to the selected word lines areincreased from Vss to a pass voltage level, such as voltage levelVpass_program.

While the voltages 1115 applied to the drain select lines are beingincreased from Vss to Vcc and the voltages 1105 applied to theunselected word lines and the voltages 1110 applied to the selected wordlines are being increased from Vss to Vpass_program, the voltage 1125 ₁applied to the selector word line 315 _(D3) in block 210 ₄ (e.g.,corresponding to the voltage SEL0 in FIGS. 5A and 11) and the voltage1125 ₂ applied to the selector word line 315 _(D4) in block 210 ₂(corresponding to the voltage SEL1 in FIGS. 5A and 11) are increasedfrom Vss to Vpass so that the selector memory cells coupled to selectorword line 315 _(D3) in block 210 ₄ and to selector word line 315 _(D4)in block 210 ₂ are activated (e.g., on). The strings of memory cellsthat include an activated selector memory cell and a target memory cellare coupled to the bit lines at Vss by the activated drain selecttransistors.

While the voltage 1125 ₁ applied to selector word line 315 _(D3) inblock 210 ₄ and the voltage 1125 ₂ applied to selector word line 315_(D4) in block 210 ₂ are being increased from Vss to Vcc, the voltages1125 ₁ applied to the selector word lines 315 _(D4), 315_(D5), and 315_(D6) in block 210 ₄ (e.g., corresponding to the voltages SEL1, SEL2,and, SEL3 in FIGS. 5A and 11) and the voltages 1125 ₂ applied toselector word lines 315 _(D3), 315_(D5), and 315 _(D6) in block 210 ₂(e.g., corresponding to the voltages SEL0, SEL2, and, SEL3 in FIGS. 5Aand 11) are maintained at Vss. This causes the selector memory cellscoupled to the selector word lines 315 _(D4), 315_(D5), and 315 _(D6)respectively in portions 240 ₂, 240 ₃, and 240 ₄ in block 210 ₄ and theselector memory cells coupled to the selector word lines 315 _(D3),315_(D5), and 315 _(D6) respectively in portions 240 ₁, 240 ₃, and 240 ₄in block 210 ₂ to be deactivated (e.g., off, FIG. 5A).

Subsequently, the voltages 1110 applied to the selected word lines inblocks 210 ₄ and 210 ₂ are increased from Vpass_program to a programmingvoltage level, such as Vprogram, while the voltages 1100 applied to thebit lines coupled to strings of memory cells having target memory cellsare at Vss, the voltages 1105 applied to the unselected word lines areat Vpass_program, the voltages 1115 applied to the drain select linesare at Vcc, and the voltages 1125 ₁ and 1125 ₂ respectively applied tothe selector word line 315 _(D3) in block 210 ₄ and the selector wordline 315 _(D4) in block 210 ₂ are at Vcc.

CONCLUSION

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Many adaptations ofthe embodiments will be apparent to those of ordinary skill in the art.Accordingly, this application is intended to cover any adaptations orvariations of the embodiments.

What is claimed is:
 1. A method of operating a memory device,comprising: sensing a target memory cell in a first block of memorycells and a target memory cell in a second block of memory cellsconcurrently while applying a read voltage to a selected access linecoupled to the target memory cell in the first block of memory cells andwhile applying a read voltage to another selected access line coupled tothe target memory cell in the second block of memory cells; wherein thetarget memory cell in the first block of memory cells and a memory cellin the second block of memory cells are each selectively coupled to afirst data line; and wherein the target memory cell in the second blockof memory cells and a memory cell in the first block of memory cells areeach selectively coupled to a second data line.
 2. The method of claim1, wherein sensing the target memory cell in the first block of memorycells and the target memory cell in the second block of memory cellsconcurrently comprises sensing the first data line selectively coupledto the target memory cell in the first block of memory cells and thesecond data line selectively coupled to the target memory cell in thesecond block of memory cells concurrently.
 3. The method of claim 2,wherein the first data line is coupled to an activated select transistorcoupled to a string of memory cells in the second block of memory cells,wherein the string of memory cells in the second block of memory cellscomprises the memory cell in the second block of memory cells andwherein the memory cell in the second block of memory cells comprises anuntargeted memory cell coupled to the selected access line coupled tothe target memory cell in the second block of memory cells and aselector memory cell that isolates the untargeted memory cell from thefirst data line.
 4. The method of claim 3, wherein the selector memorycell that isolates the untargeted memory cell from the first data lineis coupled to a selector access line in the second block of memory cellsthat receives a voltage that is insufficient to activate the selectormemory cell.
 5. The method of claim 4, wherein the selector memory cellthat isolates the untargeted memory cell from the first data lineinhibits current from flowing through the untargeted memory cell to thefirst data line.
 6. The method of claim 3, wherein the first data lineis coupled to an activated select transistor coupled to a string ofmemory cells in the first block of memory cells, wherein the string ofmemory cells in the first block of memory cells comprises the targetmemory cell in the first block of memory cells and a selector memorycell that receives a voltage that activates the selector memory cell. 7.The method of claim 1, further comprising addressing the target memorycell in the first block of memory cells and the target memory cell inthe second block of memory cells with a common page address.
 8. A methodof operating a memory device, comprising: applying a first activationvoltage to a first select line in a first block of memory cells thatactivates first and second select transistors in the first block ofmemory cells commonly coupled to the first select line, wherein thefirst select transistor is coupled to a first string of memory cells inthe first block of memory cells and to a first data line and the secondselect transistor is coupled to a second string of memory cells in thefirst block of memory cells and to a second data line; while applyingthe first activation voltage, applying a second activation voltage to asecond select line in a second block of memory cells that activatesthird and fourth select transistors in the second block of memory cellscommonly coupled to the second select line, wherein the third selecttransistor is coupled to a third string of memory cells in the secondblock of memory cells and to the first data line and the fourth selecttransistor is coupled to a fourth string of memory cells in the secondblock of memory cells and to the second data line; coupling the firststring of memory cells to the first data line while isolating the thirdstring of memory cells from the first data line and while applying thefirst and second activation voltages; and coupling the fourth string ofmemory cells to the second data line while isolating the second stringof memory cells from the second data line, and while applying the firstand second activation voltages; wherein a selector memory cell in thethird string of memory cells that is deactivated isolates the thirdstring of memory cells from the first data line and a selector memorycell in the second string of memory cells that is deactivated isolatesthe second string of memory cells from the second data line.
 9. Themethod of claim 8, wherein coupling the fourth string of memory cells tothe second data line occurs while coupling the first string of memorycells to the first data line and while isolating the third string ofmemory cells from the first data line.
 10. The method of claim 8,wherein the selector memory cell in the third string of memory cells andthe selector memory cell in the second string of memory cells are notused to store user data or ECC.
 11. The method of claim 8, furthercomprising: applying a first read voltage to a selected access linecommonly coupled to a target memory cell in the first string of memorycells and to an untargeted memory cell in the second string of memorycells while the first string is coupled to the first bit line; and whileapplying the first read voltage, applying a second read voltage toanother selected access line commonly coupled to an untargeted memorycell in the third string of memory cells and to a target memory cell inthe fourth string of memory cells while the fourth string is coupled tothe second bit line.
 12. The method of claim 11, wherein target memorycell in the first string of memory cells and the target memory cell inthe fourth string of memory cells are addressed by a common pageaddress.
 13. The method of claim 8, further comprising: applying a firstprogram voltage to a selected access line commonly coupled to a targetmemory cell in the first string of memory cells and to an untargetedmemory cell in the second string of memory cells while the first stringis coupled to the first data line; and while applying the first programvoltage, applying a second program voltage to another selected accessline commonly coupled to an untargeted memory cell in the third stringof memory cells and to a target memory cell in the fourth string ofmemory cells while the fourth string is coupled to the second data line.14. The method of claim 13, wherein the selector memory cell in thesecond string of memory cells that is deactivated maintains a voltage ona channel of the untargeted memory cell in the second string of memorycells that inhibits the untargeted memory cell in the second string ofmemory cells from being programmed, and wherein the selector memory cellin the third string of memory cells that is deactivated maintains avoltage on a channel of the untargeted memory cell in the third stringof memory cells that inhibits the untargeted memory cell in the thirdstring of memory cells from being programmed.
 15. The method of claim 8,further comprising, while applying the first and second activationvoltages: applying a first voltage to a first selector access line thatis commonly coupled to a selector memory cell in the first string ofmemory cells and the selector memory cell in the second string of memorycells, wherein the first voltage activates the selector memory cell inthe first string of memory cells and is insufficient to activate theselector memory cell in the second string of memory cells; and applyinga second voltage to a second selector access line that is commonlycoupled to the selector memory cell in the third string of memory cellsand a selector memory cell in the fourth string of memory cells whereinthe second voltage activates the selector memory cell in the fourthstring of memory cells and is insufficient to activate the selectormemory cell in the third string of memory cells.
 16. The method of claim15, wherein the selector memory cell in the first string of memory cellsand the selector memory cell in the second string of memory cells arerespectively a first selector memory cell in the first string of memorycells and a first selector memory cell in the second string of memorycells, wherein the selector memory cell in the third string of memorycells and the selector memory cell in the fourth string of memory cellsare respectively a first selector memory cell in the third string ofmemory cells and a first selector memory cell in the fourth string ofmemory cells, and further comprising, while applying the first andsecond activation voltages: applying a third voltage to a third selectoraccess line that is commonly coupled to a second selector memory cell inthe first string of memory cells and a second selector memory cell inthe second string of memory cells, wherein the third voltage activatesthe second selector memory cell in the first string of memory cells andthe second selector memory cell in the second string of memory cells;and applying a fourth voltage to a fourth selector access line that iscommonly coupled to a second selector memory cell in the third string ofmemory cells and a second selector memory cell in the fourth string ofmemory cells wherein the fourth voltage activates the second selectormemory cell in the third string of memory cells and the second selectormemory cell in the fourth string of memory cells.
 17. The method ofclaim 16, wherein the first selector memory cells in the first andfourth strings of memory cells are erased, wherein the first selectormemory cells in the second and third strings of memory cells areprogrammed, wherein the second selector memory cells in the first andfourth strings are programmed, and the second selector memory cells inthe second and third strings are erased.
 18. A method of operating amemory device, comprising: applying a first activation voltage to afirst select line in a first block of memory cells that activates firstand second select transistors in the first block of memory cellscommonly coupled to the first select line, wherein the first selecttransistor is coupled to a first string of memory cells in the firstblock of memory cells and to a first data line and the second selecttransistor is coupled to a second string of memory cells in the firstblock of memory cells and to a second data line; applying a firstvoltage to a first selector access line that is commonly coupled to aselector memory cell in the first string of memory cells and a selectormemory cell in the second string of memory cells, wherein the firstvoltage activates the selector memory cell in the first string of memorycells and is insufficient to activate the selector memory cell in thesecond string of memory cells so that the selector memory cell in thesecond string of memory cells is deactivated and isolates the secondstring of memory cells from the second data line, wherein the firststring of memory cells is coupled to the first data line through theactivated selector memory cell in the first string of memory cells andthe activated first select transistor; applying a first read voltage toa selected access line in the first block of memory cells commonlycoupled a target memory cell in the first string of memory cells and anuntargeted memory cell in the second string of memory cells; sensing thefirst data line while the first string of memory cells is coupled to thefirst data line, while the second string of memory cells is isolatedfrom the second data line, and while applying the first read voltage;applying a second activation voltage to a second select line in a secondblock of memory cells that activates third and fourth select transistorsin the second block of memory cells commonly coupled to the secondselect line, wherein the third select transistor is coupled to a thirdstring of memory cells in the second block of memory cells and to thefirst data line and the fourth select transistor is coupled to a fourthstring of memory cells in the second block of memory cells and to thesecond data line; applying a second voltage to a second selector accessline that is commonly coupled to a selector memory cell in the thirdstring of memory cells and a selector memory cell in the fourth stringof memory cells, wherein the second voltage activates the selectormemory cell in the fourth string of memory cells and is insufficient toactivate the selector memory cell in the third string of memory cells sothat the selector memory cell in the third string of memory cells isdeactivated and isolates the third string of memory cells from the firstdata line, wherein the fourth string of memory cells is coupled to thesecond data line through the activated selector memory cell in thefourth string of memory cells and the activated fourth selecttransistor; applying a second read voltage to a selected access line inthe second block of memory cells commonly coupled a target memory cellin the fourth string of memory cells and an untargeted memory cell inthe third string of memory cells; and after sensing the first data line,sensing the second data line while the fourth string of memory cells iscoupled to the second data line, while the third string of memory cellsis isolated from the first data line, and while applying the second readvoltage.
 19. The method of claim 18, further comprising charging thefirst data line before sensing the first data line and leaving thesecond data line uncharged while sensing the first data line, andcharging the second data line before sensing the second data line andleaving the first data line uncharged while sensing the second dataline.
 20. The method of claim 18, further comprising addressing thetarget memory cell in the first string of memory cells with a first pageaddress and addressing the target memory cell in the fourth string ofmemory cells with a second page address different than the first pageaddress.
 21. A method of operating a memory device, comprising: applyinga first voltage to a first selector access line commonly coupled to afirst selector memory cell in each of a first string, a second string, athird string, and a fourth string of series-coupled memory cells;applying a second voltage to a second selector access line commonlycoupled to a second selector memory cell in each of the first string,the second string, the third string, and the fourth string ofseries-coupled memory cells while applying the first voltage to thefirst selector access line; applying a third voltage to a third selectoraccess line commonly coupled to a third selector memory cell in each ofthe first string, the second string, the third string, and the fourthstring of series-coupled memory cells while applying the first voltageto the first selector access line and the second voltage to the secondselector access line; and applying a fourth voltage to a fourth selectoraccess line commonly coupled to a fourth selector memory cell in each ofthe first string, the second string, the third string, and the fourthstring of series-coupled memory cells while applying the first voltageto the first selector access line, the second voltage to the secondselector access line, and the third voltage to the third selector accessline; wherein the first voltage activates the first selector memory cellin each of the first string, the second string, the third string, andthe fourth string of series-coupled memory cells; wherein the secondvoltage activates the second selector memory cell in each of the firststring and the third string of series-coupled memory cells and isinsufficient to activate the second selector memory cell in each of thesecond string and the fourth string of series-coupled memory cells sothat the second selector memory cell in each of the second string andthe fourth string of series-coupled memory cells is deactivated; whereinthe third voltage activates the third selector memory cell in each ofthe first string, the second string, the third string, and the fourthstring of series-coupled memory cells; and wherein the fourth voltageactivates the fourth selector memory cell in each of the first stringand the second string of series-coupled memory cells and is insufficientto activate the fourth selector memory cell in each of the third stringand the fourth string of series-coupled memory cells so that the fourthselector memory cell in each of the third string and the fourth stringof series-coupled memory cells is deactivated.
 22. The method of claim21, wherein the first selector memory cell in each of the first stringand the third string of series-coupled memory cells is programmed andthe first selector memory cell in each of the second string and thefourth string of series-coupled memory cells is erased, wherein thesecond selector memory cell in each of the first string and the thirdstring of series-coupled memory cells is erased and the second selectormemory cell in each of the second string and the fourth string ofseries-coupled memory cells is programmed, wherein the third selectormemory cell in each of the first string and the second string ofseries-coupled memory cells is programmed and the third selector memorycell in each of the third string and the fourth string of series-coupledmemory cells is erased, and wherein the fourth selector memory cell ineach of the first string and the second string of series-coupled memorycells is erased and the fourth selector memory cell in each of the thirdstring and the fourth string of series-coupled memory cells isprogrammed.
 23. The method of claim 21, further comprising activating aselect transistor coupled between the first string of series-coupledmemory cells and a first data line, a select transistor coupled betweenthe second string of series-coupled memory cells and a second data line,a select transistor coupled between the third string of series-coupledmemory cells and a third data line, and a select transistor coupledbetween the fourth string of series-coupled memory cells and a fourthdata line while applying the first, second, third, and fourth voltages.24. The method of claim 23, wherein the activated first selector memorycell, the activated second selector memory cell, the activated thirdselector memory cell, and the activated fourth selector memory cell inthe first string of series-coupled memory cells couple the first stringof series-coupled memory cells to the first data line through theactivated first select transistor, wherein the second selector memorycell in the second string of series-coupled memory cells that isdeactivated isolates the second string of series-coupled memory cellsfrom the second data line, wherein the fourth selector memory cell inthe third string of series-coupled memory cells that is deactivatedisolates the third string of series-coupled memory cells from the thirddata line, and wherein the fourth selector memory cell in the fourthstring of series-coupled memory cells that is deactivated isolates thefourth string of series-coupled memory cells from the fourth data line.25. The method of claim 24, further comprising sensing the first dataline while the first string of series-coupled memory cells is coupled tothe first data line, while applying the first, second, third, and fourthvoltages, and while a read voltage is applied to an access line that iscommonly coupled to a fifth memory cell in each of the first string, thesecond string, the third string, and the fourth string of series-coupledmemory cells.
 26. A memory device, comprising: first and second blocksof memory cells; and a controller; wherein the controller is configuredto cause the memory device to sense a target memory cell in the firstblock of memory cells and a target memory cell in the second block ofmemory cells concurrently while a read voltage is being applied to aselected access line coupled to the target memory cell in the firstblock of memory cells and while a read voltage is being applied toanother selected access line coupled to the target memory cell in thesecond block of memory cells; wherein the target memory cell in thefirst block of memory cells and a memory cell in the second block ofmemory cells are each selectively coupled to a first data line; andwherein the target memory cell in the second block of memory cells and amemory cell in the first block of memory cells are each selectivelycoupled to a second data line.
 27. The memory device of claim 26,wherein the target memory cell in the first block of memory cells is ina first string of series-coupled memory cells in the first block ofmemory cells, wherein the first string of series-coupled memory cells inthe first block of memory cells is coupled to a first select transistorcoupled to the first data line, wherein the first data line is coupledto a second select transistor coupled to a first string ofseries-coupled memory cells in the second block of memory cells, whereinthe first string of series-coupled memory cells in the second block ofmemory cells comprises a memory cell coupled to the access line coupledto the target memory cell in the second block of memory cells and afirst selector memory cell, wherein the first selector memory cell isprogrammed to remain deactivated and thereby isolate the first string ofseries-coupled memory cells in the second block of memory cells from thefirst data line when the first and second select transistors areactivated and when the target memory cell in the first block of memorycells is being sensed by sensing the first data line.
 28. The memorydevice of claim 27, wherein the target memory cell in the second blockof memory cells is in a second string of series-coupled memory cells inthe second block of memory cells, wherein the second string ofseries-coupled memory cells in the second block of memory cells iscoupled to a third select transistor coupled to the second data line,wherein the second data line is coupled to a fourth select transistorcoupled to a second string of series-coupled memory cells in the firstblock of memory cells, wherein the second string of series-coupledmemory cells in the first block of memory cells comprises a memory cellcoupled to the access line coupled to the target memory cell in thefirst block of memory cells and a second selector memory cell, whereinthe second selector memory cell is programmed to remain deactivated andthereby isolate the second string of series-coupled memory cells in thefirst block of memory cells from the second data line when the first,second, third, and fourth select transistors are activated and when thetarget memory cell in the second block of memory cells is being sensedby sensing the second data line.
 29. The memory device of claim 28,wherein the first string of series-coupled memory cells in the firstblock of memory cells comprises a third selector memory cell that iscoupled to a first selector access line that is coupled to the secondselector memory cell in the second string of series-coupled memory cellsin the first block of memory cells, wherein the third selector memorycell is erased, and wherein the controller is configured to cause thememory device to apply a voltage to the first selector access line,while the first and second read voltages are being applied, thatactivates the third selector memory cell and that is insufficient toactivate the second selector memory cell.
 30. The memory device of claim29, wherein the first string of series-coupled memory cells in the firstblock of memory cells comprises a fourth selector memory cell and thesecond string of series-coupled memory cells in the first block ofmemory cells comprises a fifth selector memory cell, wherein the fourthand fifth selector memory cells are coupled to a second selector accessline, wherein the fourth selector memory cell is programmed and thefifth selector memory cell is erased, and wherein the controller isconfigured to cause the memory device to apply a voltage, while thefirst and second read voltages are being applied, to the second selectoraccess line that activates the fourth and fifth selector memory cells.31. The memory device of claim 30, wherein the second string ofseries-coupled memory cells in the second block of memory cellscomprises a sixth selector memory cell that is coupled to a thirdselector access line that is coupled to the first selector memory cellin the first string of series-coupled memory cells in the second blockof memory cells, wherein the sixth selector memory cell is erased, andwherein controller is configured to cause the memory device to apply avoltage to the third selector access line, while the first and secondread voltages are being applied, that activates the sixth selectormemory cell and that is insufficient to activate the first selectormemory cell.
 32. The memory device of claim 31, wherein the secondstring of series-coupled memory cells in the second block of memorycells comprises a seventh selector memory cell and the first string ofseries-coupled memory cells in the second block of memory cellscomprises a eighth selector memory cell, wherein the seventh and eighthselector memory cells are coupled to a fourth selector access line,wherein the seventh selector memory cell is programmed and the eighthselector memory cell is erased, and wherein the controller is configuredto cause the memory device to apply a voltage, while the first andsecond read voltages are being applied, to the fourth selector accessline that activates the seventh and eighth selector memory cells.
 33. Amemory device, comprising: first and second blocks of memory cells; anda controller; wherein the controller is configured to cause the memorydevice to apply a first activation voltage to a first select line in thefirst block of memory cells that activates first and second selecttransistors in the first block of memory cells commonly coupled to thefirst select line, wherein the first select transistor is coupled to afirst string of memory cells in the first block of memory cells and to afirst data line and the second select transistor is coupled to a secondstring of memory cells in the first block of memory cells and to asecond data line; wherein the controller is configured to cause thememory device to apply a second activation voltage, while the firstactivation voltage is applied, to a second select line in the secondblock of memory cells that activates third and fourth select transistorsin the second block of memory cells commonly coupled to the secondselect line, wherein the third select transistor is coupled to a thirdstring of memory cells in the second block of memory cells and to thefirst data line and the fourth select transistor is coupled to a fourthstring of memory cells in the second block of memory cells and to thesecond data line; wherein the controller is configured to cause thememory device to couple the first string of memory cells to the firstdata line while the third string of memory cells is isolated from thefirst data line and while the first and second activation voltages areapplied; wherein the controller is configured to cause the memory deviceto couple the fourth string of memory cells to the second data linewhile the second string of memory cells is isolated from the second dataline, while the first and second activation voltages are being applied,while the first string of memory cells is coupled to the first dataline, and while the third string of memory cells is isolated from thefirst data line; wherein a selector memory cell in the third string ofmemory cells that is deactivated isolates the third string of memorycells from the first data line and a selector memory cell in the secondstring of memory cells that is deactivated isolates the second string ofmemory cells from the second data line.
 34. The memory device of claim33, wherein the controller is configured to cause the memory device toapply a first read voltage to a selected access line commonly coupled toa target memory cell in the first string of memory cells and to anuntargeted memory cell in the second string of memory cells while thefirst string is coupled to the first data line; and wherein thecontroller is configured to cause the memory device to apply, while thefirst read voltage is applied, a second read voltage to another selectedaccess line commonly coupled to an untargeted memory cell in the thirdstring of memory cells and to a target memory cell in the fourth stringof memory cells while the fourth string is coupled to the second dataline.
 35. The memory device of claim 33, wherein the controller isconfigured to cause the memory device to apply a first program voltageto a selected access line commonly coupled to a target memory cell inthe first string of memory cells and to an untargeted memory cell in thesecond string of memory cells while the first string is coupled to thefirst data line; and wherein the controller is configured to cause thememory device to apply, while the first program voltage is applied, asecond program voltage to another selected access line commonly coupledto an untargeted memory cell in the third string of memory cells and toa target memory cell in the fourth string of memory cells while thefourth string is coupled to the second data line.
 36. The memory deviceof claim 33, wherein while the first and second activation voltages areapplied, the controller is further configured to cause the memory deviceto apply a voltage to a first selector access line that is commonlycoupled to a selector memory cell in the first string of memory cellsand the selector memory cell in the second string of memory cells,wherein the voltage applied to the first selector access line activatesthe selector memory cell in the first string of memory cells and isinsufficient to activate the selector memory cell in the second stringof memory cells; and wherein while the first and second activationvoltages are applied, the controller is further configured to cause thememory device to apply a voltage to a second selector access line thatis commonly coupled to the selector memory cell in the third string ofmemory cells and a selector memory cell in the fourth string of memorycells wherein the voltage applied to the second selector access lineactivates the selector memory cell in the fourth string of memory cellsand is insufficient to activate the selector memory cell in the thirdstring of memory cells.
 37. The memory device of claim 36, wherein theselector memory cell in the first string of memory cells is erased,wherein the selector memory cell in the second string of memory cells isprogrammed, wherein the selector memory cell in the fourth string ofmemory cells is erased, and wherein the selector memory cell in thethird string of memory cells is programmed.
 38. A memory device,comprising: first and second data lines; a first memory block comprisinga first string of series-coupled memory cells coupled to a first selecttransistor coupled to the first data line and a second string ofseries-coupled memory cells coupled to a second select transistorcoupled to the second data line; a second memory block comprising athird string of series-coupled memory cells coupled to a third selecttransistor coupled to the first data line and a fourth string ofseries-coupled memory cells coupled to a fourth select transistorcoupled to the second data line; a first selector access line in thefirst memory block commonly coupled to a first selector memory cell inthe first string of series-coupled memory cells and a first selectormemory cell in the second string of series-coupled memory cells; and asecond selector access line in the second memory block commonly coupledto a first selector memory cell in the third string of series-coupledmemory cells and a first selector memory cell in the fourth string ofseries-coupled memory cells; wherein the first selector access line isconfigured to receive a voltage that activates the first selector memorycell in the first string of series-coupled memory cells and that isinsufficient to activate the first selector memory cell in the secondstring of series-coupled memory cells so that the first selector memorycell in the second string of series-coupled memory cells isolates thesecond string of series-coupled memory cells from the second data linewhile the first, second, third and fourth select transistors areactivated and while the first string of series-coupled memory cells iscoupled to the first data line; and wherein the second selector accessline is configured to receive a voltage that activates the firstselector memory cell in the fourth string of series-coupled memory cellsand that is insufficient to activate the first selector memory cell inthe third string of series-coupled memory cells so that the firstselector memory cell in the third string of series-coupled memory cellsisolates the third string of series-coupled memory cells from the firstdata line while the first, second, third and fourth select transistorsare activated and while the first string of series-coupled memory cellsis coupled to the first data line and the fourth string ofseries-coupled memory cells is coupled to the second data line.
 39. Thememory device of claim 38, wherein the first selector cells in thefirst, second, third, and fourth strings of series-coupled memory cellsare not used to store user data or ECC.
 40. The memory device of claim38, further comprising: an access line in the first memory block,configured to receive a first read voltage, commonly coupled to anothermemory cell in the first string of series-coupled memory cells andanother selector memory cell in the second string of series-coupledmemory cells; and an access line in the second memory block, configuredto receive a second read voltage, commonly coupled to another memorycell in the third string of series-coupled memory cells and anothermemory cell in the fourth string of series-coupled memory cells; whereinthe first and second data lines are configured to be sensedconcurrently, while the first string of series-coupled memory cells iscoupled to the first data line and the fourth string of series-coupledmemory cells is coupled to the second data line, while the firstselector memory cell in the second string of series-coupled memory cellsisolates the second string of series-coupled memory cells from thesecond data line, and while the first selector memory cell in the thirdstring of series-coupled memory cells isolates the third string ofseries-coupled memory cells from the first data line.
 41. The memorydevice of claim 38, further comprising: an access line in the firstmemory block, configured to receive a first program voltage, commonlycoupled to an other memory cell in the first string of series-coupledmemory cells and an other memory cell in the second string ofseries-coupled memory cells; and an access line in the second memoryblock, configured to receive a second program voltage, commonly coupledto an other memory cell in the third string of series-coupled memorycells and an other memory cell in the fourth string of series-coupledmemory cells; wherein the first selector memory cell in the secondstring of series-coupled memory cells that isolates the second string ofseries-coupled memory cells from the second data line is configured tomaintain a voltage on a channel of the other memory cell in the secondstring of series-coupled memory cells that inhibits the other memorycell in the second string of series-coupled memory cells from beingprogrammed, and wherein the first selector memory cell in the thirdstring of series-coupled memory cells that isolates the third string ofseries-coupled memory cells from the first data line maintains a voltageon a channel of the other memory cell in the third string ofseries-coupled memory cells that inhibits the other memory cell in thethird string of series-coupled memory cells from being programmed. 42.The memory device of claim 38, further comprising: a third selectoraccess line in the first memory block commonly coupled to a secondselector memory cell in the first string of series-coupled memory cellsand a second selector memory cell in the second string of series-coupledmemory cells; and a fourth selector access line in the second memoryblock commonly coupled to a second selector memory cell in the thirdstring of series-coupled memory cells and a second selector memory cellin the fourth string of series-coupled memory cells; wherein the thirdselector access line is configured to receive a voltage that activatesthe second selector memory cell in the first string of series-coupledmemory cells and the second selector memory cell in the second string ofseries-coupled memory cells; and wherein the fourth selector access lineis configured to receive a voltage that activates the second selectormemory cell in the third string of series-coupled memory cells and thesecond selector memory cell in the fourth string of series-coupledmemory cells.
 43. An apparatus, comprising: a block of memory cellscomprising a plurality of strings of series-coupled memory cells,wherein each of the strings of series-coupled memory cells comprises aset of dummy memory cells responsive to a set of control signals and aset of data memory cells; wherein, in response to the set of controlsignals having a first set of voltages, reading of data memory cells isenabled for only a first portion of the plurality of strings ofseries-coupled memory cells; wherein, in response to the set of controlsignals having a second set of voltages, reading of data memory cells isenabled for only a second portion of the plurality of strings ofseries-coupled memory cells; and wherein, in response to the set ofcontrol signals having a third set of voltages, reading of data memorycells is enabled for the first portion and the second portion of theplurality of strings of series-coupled memory cells.
 44. The apparatusof claim 43, further comprising: wherein, in response to the set ofcontrol signals having a fourth set of voltages, reading of data memorycells is enabled for only a third portion of the plurality of strings ofseries-coupled memory cells; and wherein, in response to the set ofcontrol signals having the third set of voltages, reading of data memorycells is enabled for the first portion, the second portion and the thirdportion of the plurality of strings of series-coupled memory cells. 45.The apparatus of claim 43, further comprising: wherein the first portionof the plurality of strings of series-coupled memory cells are containedwithin a first contiguous set of strings of series-coupled memory cellsof the plurality of strings of series-coupled memory cells; and whereinthe second portion of the plurality of strings of series-coupled memorycells are contained within a second contiguous set of strings ofseries-coupled memory cells of the plurality of strings ofseries-coupled memory cells.
 46. The apparatus of claim 45, wherein thefirst portion of the plurality of strings of series-coupled memory cellscomprises every other string of series-coupled memory cells containedwithin the first contiguous set of strings of series-coupled memorycells, and wherein the second portion of the plurality of strings ofseries-coupled memory cells comprises every other string ofseries-coupled memory cells contained within the second contiguous setof strings of series-coupled memory cells.
 47. The apparatus of claim43, wherein a string of series-coupled memory cells of the first portionof the plurality of strings of series-coupled memory cells is interposedbetween strings of series-coupled memory cells of the second portion ofthe plurality of strings of series-coupled memory cells.